wishbone sram

wsram.v

module top(
	input [31:0] adr,
	input [31:0] dat_w,
	output reg [31:0] dat_r,
	input [3:0] sel,
	input cyc,
	input stb,
	output reg ack,
	input we,
	input [2:0] cti,
	input [1:0] bte,
	input err,
	input sys_clk,
	input sys_rst
);

reg [31:0] mem[0:127];

always @(posedge sys_clk) begin
	ack <= 1'd0;
	if (((cyc & stb) & ((~ack)))) begin
		ack <= 1'd1;
	end
	if (sys_rst) begin
		ack <= 1'd0;
	end
end

always @(posedge sys_clk) begin
	if ((cyc & stb) & we) begin
		if (sel[0])
			mem[adr[6:0]][7:0] <= dat_w[7:0];
		if (sel[1])
			mem[adr[6:0]][15:8] <= dat_w[15:8];
		if (sel[2])
			mem[adr[6:0]][23:16] <= dat_w[23:16];
		if (sel[3])
			mem[adr[6:0]][31:24] <= dat_w[31:24];
	end
    // if((cyc & stb) & ~we)
         dat_r <= mem[adr[6:0]];
end

endmodule