fsm.py to fsm.v - migen default

fsm.v

/* Machine-generated using Migen */
module top(
        output reg example,
        output reg [7:0] example_1,
        output fsm,
        output reg fsm_1,
        output fsm_2,
        output reg fsm_3,
        input sys_clk,
        input sys_rst
);

reg example_a0 = 1'd0;
reg example_a1 = 1'd0;
reg example_a2 = 1'd0;
reg example_a3 = 1'd0;
reg example_a4 = 1'd0;
reg example_a5 = 1'd0;
reg example_a6 = 1'd0;
reg example_example_fsm0 = 1'd0;
reg example_example_fsm1;
reg [7:0] example1_lowernext0;
reg example1_lowernext1;
reg example_example_fsm_lowernext0;
reg example_example_fsm_lowernext1;
reg basiclowerer = 1'd0;

// synthesis translate_off
reg dummy_s;
initial dummy_s <= 1'd0;
// synthesis translate_on

assign fsm_2 = ((example_example_fsm0 == 1'd0) & (~(example_example_fsm1 == 1'd0)));
assign fsm = ((~(example_example_fsm0 == 1'd0)) & (example_example_fsm1 == 1'd0));

// synthesis translate_off
reg dummy_d;
// synthesis translate_on
always @(*) begin
        example <= 1'd0;
        example_example_fsm1 <= 1'd0;
        example1_lowernext0 <= 8'd0;
        example1_lowernext1 <= 1'd0;
        example_example_fsm_lowernext0 <= 1'd0;
        example_example_fsm_lowernext1 <= 1'd0;
        example_example_fsm1 <= example_example_fsm0;
        case (example_example_fsm0)
                1'd1: begin
                        example <= 1'd0;
                        example1_lowernext0 <= (example_1 + 1'd1);
                        example1_lowernext1 <= 1'd1;
                        example_example_fsm_lowernext0 <= 7'd89;
                        example_example_fsm_lowernext1 <= 1'd1;
                        example_example_fsm1 <= 1'd0;
                end
                default: begin
                        example <= 1'd1;
                        example_example_fsm1 <= 1'd1;
                end
        endcase
// synthesis translate_off
        dummy_d <= dummy_s;
// synthesis translate_on
end

always @(posedge sys_clk) begin
        fsm_1 <= fsm;
        fsm_3 <= fsm_2;
        example_example_fsm0 <= example_example_fsm1;
        if (example1_lowernext1) begin
                example_1 <= example1_lowernext0;
        end
        if (example_example_fsm_lowernext1) begin
                basiclowerer = example_example_fsm_lowernext0;
                case (example_1)
                        1'd0: begin
                                example_a0 <= basiclowerer;
                        end
                        1'd1: begin
                                example_a1 <= basiclowerer;
                        end
                        2'd2: begin
                                example_a2 <= basiclowerer;
                        end
                        2'd3: begin
                                example_a3 <= basiclowerer;
                        end
                        3'd4: begin
                                example_a4 <= basiclowerer;
                        end
                        3'd5: begin
                                example_a5 <= basiclowerer;
                        end
                        default: begin
                                example_a6 <= basiclowerer;
                        end
                endcase
        end
        if (sys_rst) begin
                example_1 <= 8'd0;
                example_a0 <= 1'd0;
                example_a1 <= 1'd0;
                example_a2 <= 1'd0;
                example_a3 <= 1'd0;
                example_a4 <= 1'd0;
                example_a5 <= 1'd0;
                example_a6 <= 1'd0;
                fsm_1 <= 1'd1;
                fsm_3 <= 1'd0;
                example_example_fsm0 <= 1'd0;
        end
end

endmodule