bram_axil.v

bram_axil.v

module bram_axil(
    input  wire       clk,
    input  wire       rst,

    input  wire [31:0]  s_axil_awaddr,
    input  wire [2:0]  s_axil_awprot,
    input  wire        s_axil_awvaild,
    output wire        s_axil_awready,
    input  wire [31:0] s_axil_wdata,
    input  wire [3:0]  s_axil_wstrb,
    input  wire        s_axil_wvalid,
    output wire        s_axil_wready,
    output wire [1:0]  s_axil_bresp,
    output wire        s_axil_bvalid,
    input  wire        s_axil_bready,
    input  wire [31:0]  s_axil_araddr,
    input  wire [2:0]  s_axil_arprot,
    input  wire        s_axil_arvalid,
    output wire        s_axil_arready,
    output wire [31:0] s_axil_rdata,
    output wire [1:0]  s_axil_rresp,
    output wire        s_axil_rvalid,
    input  wire        s_axil_rready
);

reg s_axil_awready_reg = 1'b0, s_axil_awready_next;
reg s_axil_wready_reg = 1'b0, s_axil_wready_next;
reg s_axil_bvalid_reg = 1'b0, s_axil_bvalid_next;
reg s_axil_arready_reg = 1'b0, s_axil_arready_next;
reg [31:0] s_axil_rdata_reg = 32'd0, s_axil_rdata_next;
reg s_axil_rvalid_reg = 1'b0, s_axil_rvalid_next;

assign s_axil_awready = s_axil_awready_reg;
assign s_axil_wready = s_axil_wready_reg;
assign s_axil_bresp = 2'b00;
assign s_axil_bvalid = s_axil_bvalid_reg;
assign s_axil_arready = s_axil_arready_reg;
assign s_axil_rdata = s_axil_rdata_reg;
assign s_axil_rresp = 2'b00;
assign s_axil_rvalid = s_axil_rvalid_reg;

(* ram_style = "block" *) reg [31:0] memory [0:8191];

always @(posedge clk) begin
    s_axil_awready_reg <= s_axil_awready_next;
    s_axil_wready_reg <= s_axil_wready_next;
    s_axil_bvalid_reg <= s_axil_bvalid_next;
    s_axil_arready_reg <= s_axil_arready_next;
    s_axil_rdata_reg <= s_axil_rdata_next;
    s_axil_rvalid_reg <= s_axil_rvalid_next;

    if(rst) begin
        s_axil_awready_reg <= 1'b0;
        s_axil_wready_reg <= 1'b0;
        s_axil_bvalid_reg <= 1'b0;
        s_axil_arready_reg <= 1'b0;
        // s_axil_rdata_reg assign in other module.
        s_axil_rvalid_reg <= 1'b0;
    end
end

always @(*) begin
    s_axil_awready_next = 1'b0;
    s_axil_wready_next = 1'b0;
    s_axil_bvalid_next = s_axil_bvalid_reg && !s_axil_bready;
    s_axil_arready_next = 1'b0;
    s_axil_rvalid_next = s_axil_rvalid_reg && !s_axil_rready;

    if(s_axil_awvaild && s_axil_wvalid && !s_axil_bvalid) begin
        s_axil_awready_next = 1'b1;
        s_axil_wready_next = 1'b1;
        s_axil_bvalid_next = 1'b1;
    end
    
    if(s_axil_arvalid && !s_axil_rvalid) begin
        s_axil_arready_next = 1'b1;
        s_axil_rvalid_next = 1'b1;
    end    
end

always @(posedge clk) begin 
    if(s_axil_awvaild && s_axil_wvalid && !s_axil_bvalid) begin
        if(s_axil_wstrb[0]) memory[s_axil_awaddr[12:2]][7:0] <= s_axil_wdata[7:0];
        if(s_axil_wstrb[1]) memory[s_axil_awaddr[12:2]][15:8] <= s_axil_wdata[15:8];
        if(s_axil_wstrb[2]) memory[s_axil_awaddr[12:2]][23:16] <= s_axil_wdata[23:16];
        if(s_axil_wstrb[3]) memory[s_axil_awaddr[12:2]][31:24] <= s_axil_wdata[31:24];
    end
    
    s_axil_rdata_next <= memory[s_axil_araddr[12:2]];
end

endmodule