Alternative testbench using a lookup table

fifo_test_v2.vhd

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;

entity fifo_test_v2 is
end fifo_test_v2;

architecture rtl of fifo_test_v2 is
	--Component declaration
	component scfifo
		generic (
			add_ram_output_register	:	string := "OFF";
			allow_rwcycle_when_full	:	string := "OFF";
			almost_empty_value	:	natural := 0;
			almost_full_value	:	natural := 0;
			intended_device_family	:	string := "Cyclone IV";
			enable_ecc		:	string := "FALSE";
			lpm_numwords		:	natural;
			lpm_showahead		:	string := "OFF";
			lpm_width		:	natural;
			lpm_widthu		:	natural := 1;
			overflow_checking	:	string := "ON";
			ram_block_type		:	string := "AUTO";
			underflow_checking	:	string := "ON";
			use_eab			:	string := "ON";
			lpm_hint		:	string := "UNUSED";
			lpm_type		:	string := "scfifo"
		);
		port(
			aclr		:	in std_logic := '0';
			almost_empty	:	out std_logic;
			almost_full	:	out std_logic;
			clock		:	in std_logic;
			data		:	in std_logic_vector(lpm_width-1 downto 0);
			eccstatus	:	out std_logic_vector(1 downto 0);
			empty		:	out std_logic;
			full		:	out std_logic;
			q		:	out std_logic_vector(lpm_width-1 downto 0);
			rdreq		:	in std_logic;
			sclr		:	in std_logic := '0';
			usedw		:	out std_logic_vector(lpm_widthu-1 downto 0);
			wrreq		:	in std_logic
		);
	end component;
	
	-- internal signals
	signal aclr		:	std_logic := '0';
	signal almost_empty	:	std_logic;
	signal almost_full	:	std_logic;
	signal clock		:	std_logic;
	signal data		:	std_logic_vector(7 downto 0);
	signal eccstatus	:	std_logic_vector(1 downto 0);
	signal empty		:	std_logic;
	signal full		:	std_logic;
	signal q		:	std_logic_vector(7 downto 0);
	signal rdreq		:	std_logic;
	signal sclr		:	std_logic := '0';
	signal usedw		:	std_logic_vector(2 downto 0);
	signal wrreq		:	std_logic;	
	
	-- String padding with spaces
	function pad_string(s : string; strlen : natural) return string is
	 	variable retStr : string(1 to strlen);
	begin
  		assert strlen >= s'LENGTH report "String length must be less than strlen" severity error;
   		for n in 1 to s'HIGH loop
		    	retStr(n) := s(n);
		end loop;
 		for n in s'HIGH+1 to strlen loop
			retStr(n) := ' ';
		end loop;
	  	return retStr;
	end function pad_string;

	function str64(s : string) return string is
	begin
		return pad_string(s, 64);
	end function str64;

	--Introduce the record type (similar to a C struct)
	type test_vec_t is record
		data : std_logic_vector(7 downto 0);	-- Input data
		rdreq : std_logic;			-- rdreq input	
		wrreq : std_logic;			-- wrreq input
		sclr  : std_logic;			-- sclr  intput	
		usedw : std_logic_vector(2 downto 0);	-- Expected Output - number of used words in fifo
		q : std_logic_vector(7 downto 0);	-- Expected Output - value from last successful read
		empty : std_logic;			-- Expected Output - High when buffer is empty	
		full  : std_logic;			-- Expected Output - High when buffer is full
		msg : string(1 to 64);			-- Error string on assert failure
	end record;
	
	type lookuptable_t is array (0 to 37) of test_vec_t;
	constant tests : lookuptable_t := (
		(data => "00000000", rdreq => '0', wrreq => '0', sclr => '0', usedw => "000", q => "00000000", empty => '1', full => '0', msg=>str64("Empty buffer - no read or write")), 
		(data => "00000011", rdreq => '0', wrreq => '1', sclr => '0', usedw => "001", q => "00000000", empty => '0', full => '0', msg=>str64("Write to empty buffer") ),
		(data => "10101010", rdreq => '0', wrreq => '0', sclr => '0', usedw => "001", q => "00000000", empty => '0', full => '0', msg=>str64("Do nothing - output should still be zero") ),
		(data => "00001100", rdreq => '0', wrreq => '1', sclr => '0', usedw => "010", q => "00000000", empty => '0', full => '0', msg=>str64("Add one more word") ),
		(data => "00110000", rdreq => '0', wrreq => '1', sclr => '0', usedw => "011", q => "00000000", empty => '0', full => '0', msg=>str64("Add one more word") ),
		(data => "01010101", rdreq => '0', wrreq => '0', sclr => '0', usedw => "011", q => "00000000", empty => '0', full => '0', msg=>str64("Do nothing - output still the same") ),
		(data => "11000000", rdreq => '0', wrreq => '1', sclr => '0', usedw => "100", q => "00000000", empty => '0', full => '0', msg=>str64("Add one more word") ),
		(data => "11000000", rdreq => '1', wrreq => '0', sclr => '0', usedw => "011", q => "00000011", empty => '0', full => '0', msg=>str64("Read first word") ),
		(data => "11000000", rdreq => '1', wrreq => '0', sclr => '0', usedw => "010", q => "00001100", empty => '0', full => '0', msg=>str64("Read second word") ),
		(data => "11111111", rdreq => '1', wrreq => '1', sclr => '0', usedw => "010", q => "00110000", empty => '0', full => '0', msg=>str64("Read third word + write") ),
		(data => "11011101", rdreq => '1', wrreq => '0', sclr => '0', usedw => "001", q => "11000000", empty => '0', full => '0', msg=>str64("Read fourth word") ),
		(data => "11011101", rdreq => '1', wrreq => '0', sclr => '0', usedw => "000", q => "11111111", empty => '1', full => '0', msg=>str64("Read last word in buffer") ),
		(data => "10101010", rdreq => '0', wrreq => '1', sclr => '0', usedw => "001", q => "--------", empty => '0', full => '0', msg=>str64("Add to buffer") ),
		(data => "10101010", rdreq => '0', wrreq => '1', sclr => '0', usedw => "010", q => "--------", empty => '0', full => '0', msg=>str64("Add to buffer") ),
		(data => "10101010", rdreq => '0', wrreq => '1', sclr => '0', usedw => "011", q => "--------", empty => '0', full => '0', msg=>str64("Add to buffer") ),
		(data => "10101010", rdreq => '0', wrreq => '1', sclr => '0', usedw => "100", q => "--------", empty => '0', full => '0', msg=>str64("Add to buffer") ),
		(data => "10101010", rdreq => '0', wrreq => '1', sclr => '0', usedw => "101", q => "--------", empty => '0', full => '0', msg=>str64("Add to buffer") ),
		(data => "10101010", rdreq => '0', wrreq => '1', sclr => '0', usedw => "110", q => "--------", empty => '0', full => '0', msg=>str64("Add to buffer") ),
		(data => "10101010", rdreq => '0', wrreq => '1', sclr => '0', usedw => "111", q => "--------", empty => '0', full => '0', msg=>str64("Add to buffer") ),
		(data => "10101010", rdreq => '0', wrreq => '1', sclr => '0', usedw => "000", q => "--------", empty => '0', full => '1', msg=>str64("Buffer now full") ),
		(data => "00000000", rdreq => '0', wrreq => '1', sclr => '0', usedw => "000", q => "--------", empty => '0', full => '1', msg=>str64("Add to full buffer") ),
		(data => "11110000", rdreq => '1', wrreq => '1', sclr => '0', usedw => "111", q => "10101010", empty => '0', full => '0', msg=>str64("Read + Add with full buffer") ),
		(data => "00000000", rdreq => '1', wrreq => '0', sclr => '0', usedw => "110", q => "10101010", empty => '0', full => '0', msg=>str64("Read buffer") ),
		(data => "00000000", rdreq => '1', wrreq => '0', sclr => '0', usedw => "101", q => "10101010", empty => '0', full => '0', msg=>str64("Read buffer") ),
		(data => "00000000", rdreq => '1', wrreq => '0', sclr => '0', usedw => "100", q => "10101010", empty => '0', full => '0', msg=>str64("Read buffer") ),
		(data => "00000000", rdreq => '1', wrreq => '0', sclr => '0', usedw => "011", q => "10101010", empty => '0', full => '0', msg=>str64("Read buffer") ),
		(data => "00000000", rdreq => '1', wrreq => '0', sclr => '0', usedw => "010", q => "10101010", empty => '0', full => '0', msg=>str64("Read buffer") ),
		(data => "00000000", rdreq => '1', wrreq => '0', sclr => '0', usedw => "001", q => "10101010", empty => '0', full => '0', msg=>str64("Read buffer") ),
		(data => "00000000", rdreq => '1', wrreq => '0', sclr => '0', usedw => "000", q => "10101010", empty => '1', full => '0', msg=>str64("Read and empty buffer") ),
		(data => "11110000", rdreq => '1', wrreq => '1', sclr => '0', usedw => "001", q => "10101010", empty => '0', full => '0', msg=>str64("Read and write to an empty buffer") ),
		(data => "10111010", rdreq => '1', wrreq => '0', sclr => '0', usedw => "000", q => "11110000", empty => '1', full => '0', msg=>str64("Read last sample from buffer") ),
		(data => "00001111", rdreq => '1', wrreq => '0', sclr => '0', usedw => "000", q => "11110000", empty => '1', full => '0', msg=>str64("Read from empty buffer") ),
		-- Test sclr
		(data => "00000001", rdreq => '0', wrreq => '1', sclr => '0', usedw => "001", q => "--------", empty => '0', full => '0', msg=>str64("Write 00000001") ),
		(data => "00000010", rdreq => '0', wrreq => '1', sclr => '0', usedw => "010", q => "--------", empty => '0', full => '0', msg=>str64("Write 00000010") ),
		(data => "00000100", rdreq => '0', wrreq => '1', sclr => '0', usedw => "011", q => "--------", empty => '0', full => '0', msg=>str64("Write 00000100") ),
		(data => "00000111", rdreq => '0', wrreq => '0', sclr => '1', usedw => "000", q => "--------", empty => '1', full => '0', msg=>str64("sclr") ),
		--Does sclr take precedent over wrreq?
		(data => "00000001", rdreq => '0', wrreq => '1', sclr => '0', usedw => "001", q => "--------", empty => '0', full => '0', msg=>str64("Write 00000001") ),
		(data => "00000111", rdreq => '0', wrreq => '1', sclr => '1', usedw => "000", q => "--------", empty => '1', full => '0', msg=>str64("sclr with write") )
		
	); 

begin
--instantiate a scfifo
fifo : scfifo 
	generic map
	(
			almost_empty_value	=> 2,
			almost_full_value	=> 6,
			lpm_numwords		=> 8,
			lpm_showahead		=> "OFF",
			lpm_width		=> 8,
			lpm_widthu		=> 3,
			overflow_checking	=> "ON",
			underflow_checking	=> "ON",
			use_eab			=> "ON"
	)
	port map 
	(
			aclr		=> aclr,
			almost_empty 	=> almost_empty,	
			almost_full	=> almost_full,
			clock		=> clock,
			data		=> data,
			eccstatus	=> eccstatus,		
			empty		=> empty,	
			full		=> full,	
			q		=> q,
			rdreq		=> rdreq,	
			sclr		=> sclr,	
			usedw		=> usedw,
			wrreq		=> wrreq
	);
	

--Generate the clock
clk:	process
	begin
		clock <= '0';
		wait for 10 ns;
		for n in 1 to 64 loop
			clock <= '1';
			wait for 10 ns;		
			clock <= '0';
			wait for 10 ns;		
		end loop;

		wait;
	end process;

--Perform tests
testv:	process

	begin
		for n in tests'RANGE loop
			data	<= tests(n).data;
			rdreq	<= tests(n).rdreq;
			wrreq	<= tests(n).wrreq;
			sclr    <= tests(n).sclr;
			wait until rising_edge(clock);
			wait until falling_edge(clock);
			assert false report tests(n).msg severity note;
			assert std_match(usedw,tests(n).usedw) report "Unexpected number of words " & to_string(usedw) & " used in buffer" severity error;
			assert std_match(q,    tests(n).q)     report "Unexpected output: " & to_string(q) severity error;
			assert std_match(empty,tests(n).empty) report "Unexpected empty bit state" severity error;
			assert std_match(full, tests(n).full)  report "Unexpected full bit state" severity error;
		end loop;

		wait;


	end process;

end rtl;