penguin2716

#!/bin/bash
#
# asetroot.sh
#
# Copyright (c) 2014 Takuma Nakajima
#  
# This software is released under the MIT License.
# http://opensource.org/licenses/mit-license.php
# 

deltam

; Googleグループ clojure-ja
; 質問: 関数型プログラミングでいうZip関数をClojureではどう書く？
; <http://groups.google.com/group/clojure-ja/browse_thread/thread/98cc4e3b7bcb4a28#>
; それぞれREPL実行結果まとめ

(def a [1 2 3 4])
(def b [5 6 7 8])


; はやみずさんのアイデア

unarist

/* ==UserStyle==
@name           Mastodon - Hide private posts
@namespace      github.com/unarist
@version        1.0.0
@description    Hide private posts from timeline
@author         unarist
==/UserStyle== */

@-moz-document regexp("^https://[^/]+/web/.*") {
  /* :not(.muted) filters notification */

Th3Fanbus

https://review.coreboot.org/c/coreboot/+/46943 cpu/intel/Makefile.inc: Use correct Kconfig symbols https://review.coreboot.org/c/coreboot/+/46977 sb/intel/lynxpoint: Use common code to generate HPET table https://review.coreboot.org/c/coreboot/+/46719 sb/intel/lynxpoint: Drop unnecessary 'UL' suffix https://review.coreboot.org/c/coreboot/+/46720 {cpu,nb}/intel/haswell: Drop unnecessary 'UL' suffix https://review.coreboot.org/c/coreboot/+/46725 sb/intel/lynxpoint/lpc.c: Simplify PM init sequence https://review.coreboot.org/c/coreboot/+/46726 sb/intel/lynxpoint: Align with Broadwell https://review.coreboot.org/c/coreboot/+/46727 azalia: Treat all negative return values as errors https://review.coreboot.org/c/coreboot/+/46728 azalia: Use 'HDA_GCTL_CRST' macro as unset-mask https://review.coreboot.org/c/coreboot/+/46734 Revert "broadwell: Switch to using common ACPI _SWS code" https://review.coreboot.org/c/coreboot/+/46732 soc/intel/broadwell/gma.c: Align struct with Haswell

ArthurHeymans

How to flash coreboot to the thinkpad x60 the proper way

-> https://blog.aheymans.xyz/old-how-to-flash-coreboot-to-the-thinkpad-x60-the-proper-way/ is more up to date

What is so special about the x60 when running vendor bios?

Vendor BIOS write protects its bootblock, which means the lowest 64K of the flash can't be modified

This is a problem since the first code that runs on the CPU comes from there and if we ever want to run coreboot the cpu must start with coreboot code. This write protection is set in the PBR (protect bios range) registers on the southbridge, there is currently no known way to change them back once they are locked by setting the SPI Configuration Lock-Down bit.

voluntas

WebRTC の今

日時:	2019-03-13
作:	@voluntas
バージョン:	19.03.0
url:	https://voluntas.github.io/

kazuho

#! /usr/bin/perl
#
# Written in 2017 by Kazuho Oku
#
# To the extent possible under law, the author(s) have dedicated all copyright and related and neighboring rights to this software to the public domain worldwide. This software is distributed without any warranty.
# You should have received a copy of the CC0 Public Domain Dedication along with this software. If not, see <http://creativecommons.org/publicdomain/zero/1.0/>.
# 
use strict;
use warnings;

mikelei8291

Deprecated

Hosted at new repo: https://github.com/mikelei8291/Userscripts/blob/master/pixiv-fanbox-downloader/script.js

dherman

Original paper on A-normal form:

http://redlinernotes.com/docs/Classics/The%20Essence%20of%20Compiling%20with%20Continuations.pdf

A high-level intro to ANF:

http://matt.might.net/articles/a-normalization/

One of the earlier attempts to relate SSA and CPS:

kayceesrk

Concurrency primitives

Signature

(* raw continuation *)
type ('a,'b) stack
perform  : 'a eff -> 'a
resume   : ('a,'b) stack -> ('c -> 'a) -> 'c -> 'b
delegate : 'a eff -> ('a,'b) stack -> 'b