PLL_MIPI set_rate

gistfile1.txt

diff --git a/drivers/gpu/drm/sun4i/sun6i_mipi_dphy.c b/drivers/gpu/drm/sun4i/sun6i_mipi_dphy.c
index e4d19431fa0e..31f74477b5f6 100644
--- a/drivers/gpu/drm/sun4i/sun6i_mipi_dphy.c
+++ b/drivers/gpu/drm/sun4i/sun6i_mipi_dphy.c
@@ -86,6 +86,9 @@ int sun6i_dphy_init(struct sun6i_dphy *dphy, unsigned int lanes)
 	reset_control_deassert(dphy->reset);
 	clk_prepare_enable(dphy->mod_clk);
 	clk_set_rate_exclusive(dphy->mod_clk, 150000000);
+	clk_prepare_enable(dphy->pll_mipi_clk);
+	clk_set_rate_exclusive(dphy->pll_mipi_clk, 180000000);
 
 	regmap_write(dphy->regs, SUN6I_DPHY_TX_CTL_REG,
 		     SUN6I_DPHY_TX_CTL_HS_TX_CLK_CONT);
@@ -192,7 +195,9 @@ int sun6i_dphy_power_off(struct sun6i_dphy *dphy)
 int sun6i_dphy_exit(struct sun6i_dphy *dphy)
 {
 	clk_rate_exclusive_put(dphy->mod_clk);
+	clk_rate_exclusive_put(dphy->pll_mipi_clk);
 	clk_disable_unprepare(dphy->mod_clk);
+	clk_disable_unprepare(dphy->pll_mipi_clk);
 	reset_control_assert(dphy->reset);
 
 	return 0;
@@ -267,6 +272,13 @@ int sun6i_dphy_probe(struct sun6i_dsi *dsi, struct device_node *node)
 		goto err_free_bus;
 	}
 
+	dphy->pll_mipi_clk = of_clk_get_by_name(node, "pll-mipi");
+	if (IS_ERR(dphy->pll_mipi_clk)) {
+		dev_err(dsi->dev, "Couldn't get the PLL_MIPI clock\n");
+		ret = PTR_ERR(dphy->pll_mipi_clk);
+		goto err_free_bus;
+	}
+
 	dsi->dphy = dphy;
 
 	return 0;
@@ -284,6 +296,7 @@ int sun6i_dphy_remove(struct sun6i_dsi *dsi)
 	struct sun6i_dphy *dphy = dsi->dphy;
 
 	regmap_mmio_detach_clk(dphy->regs);
+	clk_put(dphy->pll_mipi_clk);
 	clk_put(dphy->mod_clk);
 	clk_put(dphy->bus_clk);
 	reset_control_put(dphy->reset);