openedev

[    1.783994] sun6i-mipi-dsi 1ca0000.dsi: Attached device fy07024di26a30d
[    1.820892] sun4i-drm display-engine: bound 1100000.mixer (ops sun8i_mixer_ops)
[    1.830196] sun4i-drm display-engine: bound 1200000.mixer (ops sun8i_mixer_ops)
[    1.837718] sun4i_dclk_recalc_rate: val = 1, rate = 588000000
[    1.843717] sun4i-drm display-engine: No panel or bridge found... RGB output disabled
[    1.851577] sun4i-drm display-engine: bound 1c0c000.lcd-controller (ops sun4i_tcon_ops)
[    1.859791] sun4i-drm display-engine: bound 1c0d000.lcd-controller (ops sun4i_tcon_ops)
[    1.867820] 0.0 drm_connector_init
[    1.871237] 0. 282992392-1-0 (null)
[    1.874737] 0.1 drm_connector_init

openedev

diff --git a/drivers/gpu/drm/sun4i/sun4i_dotclock.c b/drivers/gpu/drm/sun4i/sun4i_dotclock.c
index 778562b31598..56ef24b21448 100644
--- a/drivers/gpu/drm/sun4i/sun4i_dotclock.c
+++ b/drivers/gpu/drm/sun4i/sun4i_dotclock.c
@@ -75,11 +75,11 @@ static long sun4i_dclk_round_rate(struct clk_hw *hw, unsigned long rate,
 	struct sun4i_tcon *tcon = dclk->tcon;
 	unsigned long best_parent = 0;
 	u8 best_div = 1;
+	u64 ideal = (u64)rate * tcon->dclk_mul;
 	int i;

openedev

LOOP0. rank 2, channel 0

LOOP0. rank 2, channel 1

LOOP1. rank 2, ch 0

LOOP0. rank 1, channel 0

LOOP0. rank 1, channel 1

openedev

static int sdram_init(struct dram_info *dram,
		      struct rk3399_sdram_params *sdram_params)
{
	unsigned char dramtype = sdram_params->base.dramtype;
	unsigned int ddr_freq = sdram_params->base.ddr_freq;
	u32 training_flag = PI_READ_GATE_TRAINING;
	int channel, ch;
	u32 rank;
	int ret;

openedev

static int sdram_init(struct dram_info *dram,
		      struct rk3399_sdram_params *sdram_params)
{
	unsigned char dramtype = sdram_params->base.dramtype;
	unsigned int ddr_freq = sdram_params->base.ddr_freq;
	u32 training_flag = PI_READ_GATE_TRAINING;
	int channel, ch;
	u32 rank;
	int ret;

openedev

diff --git a/Makefile b/Makefile
index 92e04dd689..e7f68d63c7 100644
--- a/Makefile
+++ b/Makefile
@@ -851,6 +851,11 @@ ifeq ($(CONFIG_ARCH_SUNXI)$(CONFIG_SPL),yy)
 ALL-y += u-boot-sunxi-with-spl.bin
 endif
 
+# Build a combined spl + u-boot image for rockchip
+ifdef CONFIG_ROCKCHIP_RK3399

openedev

[   10.364112] lcd_clk_config: dsi_div = 6, tcon_div = 4, lcd_div = 1
[   10.364119] lcd_clk_config: lcd_dclk_freq = 148, dclk_rate = 148000000
[   10.364125] lcd_clk_config: lcd_rate = 888000000, pll_rate = 888000000, dsi_rate = 148000000
[   10.364134] get_factors_pll_mipi: rate = 888000000, parent = 297000000
[   10.364139] get_factors_pll_mipi: tmp_rate = 888000000
[   10.364143] get_factors_pll_mipi: want_rate = 888
[   10.364158] n=0, k=2, m=0
[   10.364167] get_factors_pll_mipi: rate = 891000000, parent = 297000000
[   10.364172] get_factors_pll_mipi: tmp_rate = 891000000
[   10.364176] get_factors_pll_mipi: want_rate = 891

openedev

diff --git a/drivers/video/sunxi/disp2/disp/de/disp_lcd.c b/drivers/video/sunxi/disp2/disp/de/disp_lcd.c
index e8b651e1571..d6a76e51283 100755
--- a/drivers/video/sunxi/disp2/disp/de/disp_lcd.c
+++ b/drivers/video/sunxi/disp2/disp/de/disp_lcd.c
@@ -790,18 +790,29 @@ static s32 lcd_clk_config(struct disp_device* lcd)
 	}
 	dsi_rate = pll_rate / clk_info.dsi_div;
 
+	printk("lcd_clk_config: dsi_div = %d, tcon_div = %d, lcd_div = %d\n",
+		clk_info.dsi_div, clk_info.tcon_div, clk_info.lcd_div);

openedev

+       printf("MMC%d: %p = 0x%x, %p = 0x%x, %p = 0x%x\n", priv->mmc_no, gate_reg,
+               readl(gate_reg), priv->mclkreg, readl(priv->mclkreg),
+               reset_reg, readl(reset_reg));
+
        ret = mmc_set_mod_clk(priv, 24000000);

openedev

commit 8427f6b2b471ed7a05d922b17f96bf5510a7add2
Author: Jagan Teki <jagan@amarulasolutions.com>
Date:   Fri Jan 11 18:00:56 2019 +0530

    media: sun6i: Add mod_rate quirk
    
    Unfortunately default CSI_SCLK rate cannot work properly to
    drive the connected sensor interface, particularly on few
    Allwinner SoC's like A64.