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commit 8427f6b2b471ed7a05d922b17f96bf5510a7add2
Author: Jagan Teki <jagan@amarulasolutions.com>
Date: Fri Jan 11 18:00:56 2019 +0530
media: sun6i: Add mod_rate quirk
Unfortunately default CSI_SCLK rate cannot work properly to
drive the connected sensor interface, particularly on few
Allwinner SoC's like A64.
unsigned int *p = 0x1c20000;
unsigned int *q;
unsigned char ch = 0x60;
q = p + ch;
// q = (void *)p + ch;
printf("%p\n", q);
@openedev
openedev / gist:e76ef26f75f133883f295225efb5b4bd
Created January 9, 2019 11:27
A10 MMC bug - u-boot-2019.01
diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c
index 9bf040cb40..490a27b038 100644
--- a/drivers/mmc/sunxi_mmc.c
+++ b/drivers/mmc/sunxi_mmc.c
@@ -19,6 +19,13 @@
#include <asm/arch/mmc.h>
#include <asm-generic/gpio.h>
+#ifdef CONFIG_DM_MMC
+struct sunxi_mmc_variant {
@openedev
openedev / gist:a7caad92033ee2b2981bcef3a8204995
Created January 9, 2019 11:26
A10 MMC bug- uboot-2019.01
diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c
index 9bf040cb40..490a27b038 100644
--- a/drivers/mmc/sunxi_mmc.c
+++ b/drivers/mmc/sunxi_mmc.c
@@ -19,6 +19,13 @@
#include <asm/arch/mmc.h>
#include <asm-generic/gpio.h>
+#ifdef CONFIG_DM_MMC
+struct sunxi_mmc_variant {
diff --git a/drivers/gpu/drm/sun4i/sun6i_mipi_dphy.c b/drivers/gpu/drm/sun4i/sun6i_mipi_dphy.c
index e4d19431fa0e..31f74477b5f6 100644
--- a/drivers/gpu/drm/sun4i/sun6i_mipi_dphy.c
+++ b/drivers/gpu/drm/sun4i/sun6i_mipi_dphy.c
@@ -86,6 +86,9 @@ int sun6i_dphy_init(struct sun6i_dphy *dphy, unsigned int lanes)
reset_control_deassert(dphy->reset);
clk_prepare_enable(dphy->mod_clk);
clk_set_rate_exclusive(dphy->mod_clk, 150000000);
+ clk_prepare_enable(dphy->pll_mipi_clk);
+ clk_set_rate_exclusive(dphy->pll_mipi_clk, 180000000);
diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
index 1b4192ed6ab5..b3e794a4aadf 100644
--- a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
+++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
@@ -167,7 +167,7 @@ static struct ccu_nkm pll_mipi_clk = {
.n = _SUNXI_CCU_MULT(8, 4),
.k = _SUNXI_CCU_MULT_MIN(4, 2, 2),
.m = _SUNXI_CCU_DIV(0, 4),
- .min_rate = 500000000,
+ .min_rate = 300000000,