gistfile1.vhdl

if (rising_edge(clk)) then
    counter := counter + 1;
    if (sensor_mem /= sensor_in and sensor_in = '1') then
        if (counter_trigger < (counter - 10)) then
            hold_counter := hold_counter + 1;
        end if;
        if (counter_trigger > (counter + 10)) then
        	hold_counter := 0;
        end if;
    
        counter := 0;
    end if;
    sensor_mem := sensor_in;

    if (hold_counter >= hold_time) then
        sensor_out <= '1';
    else
        sensor_out <= '0';
    end if;
end if;