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Willem Melching pd0wm

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View sonata.py
import time
import struct
from panda import Panda
from hexdump import hexdump
from panda.python.isotp import isotp_send, isotp_recv
BUS = 1
panda = Panda()
panda.set_safety_mode(Panda.SAFETY_ELM327)
@pd0wm
pd0wm / terminator.conf
Created May 10, 2019
Terminator config
View terminator.conf
[global_config]
inactive_color_offset = 1
[profiles]
[[default]]
use_system_font = False
font = Source Code Pro For Powerline 11
palette = "#073642:#dc322f:#859900:#b58900:#268bd2:#d33682:#2aa198:#eee8d5:#586e75:#cb4b16:#586e75:#657b83:#839496:#6c71c4:#93a1a1:#fdf6e3"
foreground_color = "#eee8d5"
View flipflops
Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST |
=====================================================================================
| cur_timer_2_reset_reg | Flip-flop | 1 | N | N | N | N | N | N | N |
| cur_state_reg | Flip-flop | 6 | Y | N | N | N | Y | N | N |
| cur_piece_reg | Flip-flop | 3 | Y | N | N | N | N | N | N |
| cur_x_reg | Flip-flop | 3 | Y | N | N | N | N | N | N |
| cur_y_reg | Flip-flop | 4 | Y | N | N | N | N | N | N |
| cur_y_new_reg | Flip-flop | 4 | Y | N | N | N | N | N | N |
| cur_rot_reg | Flip-flop | 2 | Y | N | N | N | N | N | N |
| lut_x_reg | Flip-flop | 3 | Y | N | N | N | N | N | N |
View gist:7759769
#*********************************************************
# synthesize script for cell: controller *
#*********************************************************
set hdlin_vhdl_93 false
set hdlin_ff_always_async_set_reset true
set hdlin_ff_always_sync_set_reset true
set vhdlout_architecture_name "synthesised"
set vhdlout_use_packages {"ieee.std_logic_1164" "CellsLib.CellsLib_DECL_PACK"}
set company "ontwerp_practicum"
set designer "epo3-user"
View gist:7756315
#*********************************************************
# synthesize script for cell: controller *
#*********************************************************
set hdlin_vhdl_93 false
set hdlin_ff_always_async_set_reset true
set hdlin_ff_always_sync_set_reset true
set vhdlout_architecture_name "synthesised"
set vhdlout_use_packages {"ieee.std_logic_1164" "CellsLib.CellsLib_DECL_PACK"}
set company "ontwerp_practicum"
set designer "epo3-user"
View gist:5763853
if (rising_edge(clk)) then
tick_counter := tick_counter + 1;
if (sensor_mem /= sensor_in and sensor_in = '1') then
if (measure = 1) then
if (i < 2) then -- the number of ticks in a frequency will be measured X times
sum := sum + tick_counter;
i := i + 1;
elsif (i = 2) then
counter_trigger := sum / 2; -- average ticks
sum := 0;
View gist:5763830
if (rising_edge(clk)) then
counter := counter + 1;
if (sensor_mem /= sensor_in and sensor_in = '1') then
if (counter_trigger < (counter - 10)) then
hold_counter := hold_counter + 1;
end if;
if (counter_trigger > (counter + 10)) then
hold_counter := 0;
end if;