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gistfile1.txt
#*********************************************************
# synthesize script for cell: controller *
#*********************************************************
set hdlin_vhdl_93 false
set hdlin_ff_always_async_set_reset true
set hdlin_ff_always_sync_set_reset true
set vhdlout_architecture_name "synthesised"
set vhdlout_use_packages {"ieee.std_logic_1164" "CellsLib.CellsLib_DECL_PACK"}
set company "ontwerp_practicum"
set designer "epo3-user"
set target_library {"/data/public/common/software/opprog/synth_libs/g_digilib5_99.db"}
set link_library [list "*" "/data/public/common/software/opprog/synth_libs/g_digilib5_99.db" "/data/public/common/software/opprog/synth_libs/g_analib8_00.db" "/data/public/common/software/opprog/synth_libs/buffers.db"]
define_design_lib MY_LIB -path ./syn_work
define_design_lib CELLSLIB -path /data/public/common/software/opprog/synth_libs/CellsLib
read_file -format vhdl -work MY_LIB VHDL/params.vhd
read_file -format vhdl -work MY_LIB {VHDL/controller.vhd VHDL/controller-controller_arch.vhd}
set_dont_touch {g_analib8_00/*}
# set_max_fanout 1.8 all_inputs()
# set_max_area 1000
set compile_preserve_subdesign_interfaces true
compile
ungroup -all -flat
report_area
report_fsm
write_file -f ddc controller -output ./ADB/controller.ddc
write_file -f vhdl controller -output ./VHDL/controller_SYNTH.vhd
quit
----- invoking synthesizer .....
Design Compiler Graphical
DC Ultra (TM)
DFTMAX (TM)
Power Compiler (TM)
DesignWare (R)
DC Expert (TM)
Design Vision (TM)
HDL Compiler (TM)
VHDL Compiler (TM)
DFT Compiler
Library Compiler (TM)
Design Compiler(R)
Version G-2012.06 for RHEL32 -- May 30, 2012
Copyright (c) 1988-2012 Synopsys, Inc.
This software and the associated documentation are confidential and
proprietary to Synopsys, Inc. Your use or disclosure of this software
is subject to the terms and conditions of a written license agreement
between you, or your company, and Synopsys, Inc.
Initializing...
#*********************************************************
# synthesize script for cell: controller *
#*********************************************************
set hdlin_vhdl_93 false
false
set hdlin_ff_always_async_set_reset true
true
set hdlin_ff_always_sync_set_reset true
true
set vhdlout_architecture_name "synthesised"
synthesised
set vhdlout_use_packages {"ieee.std_logic_1164" "CellsLib.CellsLib_DECL_PACK"}
"ieee.std_logic_1164" "CellsLib.CellsLib_DECL_PACK"
set company "ontwerp_practicum"
ontwerp_practicum
set designer "epo3-user"
epo3-user
set target_library {"/data/public/common/software/opprog/synth_libs/g_digilib5_99.db"}
"/data/public/common/software/opprog/synth_libs/g_digilib5_99.db"
set link_library [list "*" "/data/public/common/software/opprog/synth_libs/g_digilib5_99.db" "/data/public/common/software/opprog/synth_libs/g_analib8_00.db" "/data/public/common/software/opprog/synth_libs/buffers.db"]
* /data/public/common/software/opprog/synth_libs/g_digilib5_99.db /data/public/common/software/opprog/synth_libs/g_analib8_00.db /data/public/common/software/opprog/synth_libs/buffers.db
define_design_lib MY_LIB -path ./syn_work
1
define_design_lib CELLSLIB -path /data/public/common/software/opprog/synth_libs/CellsLib
1
read_file -format vhdl -work MY_LIB VHDL/params.vhd
Loading db file '/data/public/common/software/opprog/synth_libs/g_digilib5_99.db'
Loading db file '/data/public/common/software/opprog/synth_libs/g_analib8_00.db'
Loading db file '/data/public/common/software/opprog/synth_libs/buffers.db'
Loading db file '/data/public/common/software/synopsys/G-2012.06/libraries/syn/gtech.db'
Loading db file '/data/public/common/software/synopsys/G-2012.06/libraries/syn/standard.sldb'
Loading link library 'g_digilib5_99'
Loading link library 'g_analib8_00'
Loading link library 'buffers'
Loading link library 'gtech'
Loading vhdl file '/home/epo3-user/Desktop/epo3/master/VHDL/params.vhd'
Running PRESTO HDLC
Compiling Package Declaration VGA_PARAMS
Compiling Package Body VGA_PARAMS
No designs were read
read_file -format vhdl -work MY_LIB {VHDL/controller.vhd VHDL/controller-controller_arch.vhd}
Loading vhdl files: '/home/epo3-user/Desktop/epo3/master/VHDL/controller.vhd' '/home/epo3-user/Desktop/epo3/master/VHDL/controller-controller_arch.vhd'
Running PRESTO HDLC
-- Compiling Source File /home/epo3-user/Desktop/epo3/master/VHDL/controller.vhd
Compiling Entity Declaration CONTROLLER
-- Compiling Source File /home/epo3-user/Desktop/epo3/master/VHDL/controller-controller_arch.vhd
Compiling Architecture CONTROLLER_ARCH of CONTROLLER
Statistics for case statements in always block at line 28 in file
'/home/epo3-user/Desktop/epo3/master/VHDL/controller-controller_arch.vhd'
===============================================
| Line | full/ parallel |
===============================================
| 30 | auto/auto |
===============================================
Inferred memory devices in process
in routine controller line 17 in file
'/home/epo3-user/Desktop/epo3/master/VHDL/controller-controller_arch.vhd'.
===============================================================================
| Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
| cur_state_reg | Flip-flop | 6 | Y | N | N | N | Y | N | N |
===============================================================================
Inferred memory devices in process
in routine controller line 28 in file
'/home/epo3-user/Desktop/epo3/master/VHDL/controller-controller_arch.vhd'.
=============================================================================
| Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST |
=============================================================================
| new_y_reg | Latch | 4 | Y | N | N | N | - | - | - |
| lut_x_reg | Latch | 3 | Y | N | N | N | - | - | - |
| lut_y_reg | Latch | 4 | Y | N | N | N | - | - | - |
| lut_rot_reg | Latch | 2 | Y | N | N | N | - | - | - |
| lut_piece_type_reg | Latch | 3 | Y | N | N | N | - | - | - |
| lut_start_reg | Latch | 1 | N | N | N | N | - | - | - |
| new_piece_reg | Latch | 1 | N | N | N | N | - | - | - |
| check_start_reg | Latch | 1 | N | N | N | N | - | - | - |
| draw_erase_draw_reg | Latch | 1 | N | N | N | N | - | - | - |
| draw_erase_start_reg | Latch | 1 | N | N | N | N | - | - | - |
| clear_shift_start_reg | Latch | 1 | N | N | N | N | - | - | - |
| draw_score_draw_reg | Latch | 1 | N | N | N | N | - | - | - |
| timer_1_time_reg | Latch | 8 | Y | N | N | N | - | - | - |
| timer_1_start_reg | Latch | 1 | N | N | N | N | - | - | - |
| timer_2_time_reg | Latch | 8 | Y | N | N | N | - | - | - |
| timer_2_start_reg | Latch | 1 | N | N | N | N | - | - | - |
| cur_piece_reg | Latch | 3 | Y | N | N | N | - | - | - |
| next_state_reg | Latch | 6 | Y | N | N | N | - | - | - |
| cur_x_reg | Latch | 3 | Y | N | N | N | - | - | - |
| cur_y_reg | Latch | 4 | Y | N | N | N | - | - | - |
| timer_1_reset_reg | Latch | 1 | N | N | N | N | - | - | - |
| timer_2_reset_reg | Latch | 1 | N | N | N | N | - | - | - |
=============================================================================
Presto compilation completed successfully.
Current design is now '/home/epo3-user/Desktop/epo3/master/VHDL/controller.db:controller'
Loaded 1 design.
Current design is 'controller'.
controller
set_dont_touch {g_analib8_00/*}
1
# set_max_fanout 1.8 all_inputs()
# set_max_area 1000
set compile_preserve_subdesign_interfaces true
true
compile
Information: Evaluating DesignWare library utilization. (UISN-27)
============================================================================
| DesignWare Building Block Library | Version | Available |
============================================================================
| Basic DW Building Blocks | G-2012.06-DWBB_201206.0 | * |
| Licensed DW Building Blocks | | |
============================================================================
Information: There are 2 potential problems in your design. Please run 'check_design' for more information. (LINT-99)
Beginning Pass 1 Mapping
------------------------
Processing 'controller'
Information: The register 'timer_2_time_reg[7]' is a constant and will be removed. (OPT-1206)
Information: The register 'timer_2_time_reg[6]' is a constant and will be removed. (OPT-1206)
Information: The register 'timer_2_time_reg[1]' is a constant and will be removed. (OPT-1206)
Information: The register 'timer_2_time_reg[0]' is a constant and will be removed. (OPT-1206)
Information: The register 'draw_score_draw_reg' is a constant and will be removed. (OPT-1206)
Information: The register 'timer_1_time_reg[0]' is a constant and will be removed. (OPT-1206)
Information: The register 'timer_1_time_reg[1]' is a constant and will be removed. (OPT-1206)
Information: The register 'timer_1_time_reg[6]' is a constant and will be removed. (OPT-1206)
Information: The register 'timer_1_time_reg[7]' is a constant and will be removed. (OPT-1206)
Information: The register 'lut_rot_reg[1]' is a constant and will be removed. (OPT-1206)
Information: The register 'lut_rot_reg[0]' is a constant and will be removed. (OPT-1206)
Information: The register 'cur_x_reg[2]' is a constant and will be removed. (OPT-1206)
Information: The register 'lut_x_reg[2]' is a constant and will be removed. (OPT-1206)
Information: The register 'cur_x_reg[1]' is a constant and will be removed. (OPT-1206)
Information: The register 'cur_x_reg[0]' is a constant and will be removed. (OPT-1206)
Warning: Target library contains no replacement for register 'next_state_reg[0]' (**FFGEN**). (TRANS-4)
Warning: Target library contains no replacement for register 'next_state_reg[1]' (**FFGEN**). (TRANS-4)
Warning: Target library contains no replacement for register 'next_state_reg[3]' (**FFGEN**). (TRANS-4)
Warning: Target library contains no replacement for register 'next_state_reg[5]' (**FFGEN**). (TRANS-4)
Warning: Target library contains no replacement for register 'next_state_reg[4]' (**FFGEN**). (TRANS-4)
Warning: Target library contains no replacement for register 'next_state_reg[2]' (**FFGEN**). (TRANS-4)
Warning: Target library contains no replacement for register 'timer_2_start_reg' (**FFGEN**). (TRANS-4)
Warning: Target library contains no replacement for register 'draw_erase_draw_reg' (**FFGEN**). (TRANS-4)
Warning: Target library contains no replacement for register 'check_start_reg' (**FFGEN**). (TRANS-4)
Warning: Target library contains no replacement for register 'timer_2_time_reg[5]' (**FFGEN**). (TRANS-4)
Warning: Target library contains no replacement for register 'timer_2_time_reg[4]' (**FFGEN**). (TRANS-4)
Warning: Target library contains no replacement for register 'timer_2_time_reg[3]' (**FFGEN**). (TRANS-4)
Warning: Target library contains no replacement for register 'timer_2_time_reg[2]' (**FFGEN**). (TRANS-4)
Warning: Target library contains no replacement for register 'clear_shift_start_reg' (**FFGEN**). (TRANS-4)
Warning: Target library contains no replacement for register 'new_piece_reg' (**FFGEN**). (TRANS-4)
Warning: Target library contains no replacement for register 'cur_piece_reg[2]' (**FFGEN**). (TRANS-4)
Warning: Target library contains no replacement for register 'cur_piece_reg[1]' (**FFGEN**). (TRANS-4)
Warning: Target library contains no replacement for register 'cur_piece_reg[0]' (**FFGEN**). (TRANS-4)
Warning: Target library contains no replacement for register 'timer_1_time_reg[5]' (**FFGEN**). (TRANS-4)
Warning: Target library contains no replacement for register 'timer_1_time_reg[4]' (**FFGEN**). (TRANS-4)
Warning: Target library contains no replacement for register 'timer_1_time_reg[3]' (**FFGEN**). (TRANS-4)
Warning: Target library contains no replacement for register 'timer_1_time_reg[2]' (**FFGEN**). (TRANS-4)
Warning: Target library contains no replacement for register 'timer_1_start_reg' (**FFGEN**). (TRANS-4)
Warning: Target library contains no replacement for register 'draw_erase_start_reg' (**FFGEN**). (TRANS-4)
Warning: Target library contains no replacement for register 'lut_start_reg' (**FFGEN**). (TRANS-4)
Warning: Target library contains no replacement for register 'lut_piece_type_reg[0]' (**FFGEN**). (TRANS-4)
Warning: Target library contains no replacement for register 'lut_piece_type_reg[1]' (**FFGEN**). (TRANS-4)
Warning: Target library contains no replacement for register 'lut_piece_type_reg[2]' (**FFGEN**). (TRANS-4)
Warning: Target library contains no replacement for register 'lut_x_reg[1]' (**FFGEN**). (TRANS-4)
Warning: Target library contains no replacement for register 'lut_x_reg[0]' (**FFGEN**). (TRANS-4)
Warning: Target library contains no replacement for register 'cur_y_reg[0]' (**FFGEN**). (TRANS-4)
Warning: Target library contains no replacement for register 'new_y_reg[1]' (**FFGEN**). (TRANS-4)
Warning: Target library contains no replacement for register 'cur_y_reg[1]' (**FFGEN**). (TRANS-4)
Warning: Target library contains no replacement for register 'lut_y_reg[1]' (**FFGEN**). (TRANS-4)
Warning: Target library contains no replacement for register 'new_y_reg[2]' (**FFGEN**). (TRANS-4)
Warning: Target library contains no replacement for register 'cur_y_reg[2]' (**FFGEN**). (TRANS-4)
Warning: Target library contains no replacement for register 'lut_y_reg[2]' (**FFGEN**). (TRANS-4)
Warning: Target library contains no replacement for register 'new_y_reg[3]' (**FFGEN**). (TRANS-4)
Warning: Target library contains no replacement for register 'cur_y_reg[3]' (**FFGEN**). (TRANS-4)
Warning: Target library contains no replacement for register 'lut_y_reg[3]' (**FFGEN**). (TRANS-4)
Warning: Target library contains no replacement for register 'new_y_reg[0]' (**FFGEN**). (TRANS-4)
Warning: Target library contains no replacement for register 'lut_y_reg[0]' (**FFGEN**). (TRANS-4)
Warning: Target library contains no replacement for register 'timer_1_reset_reg' (**FFGEN**). (TRANS-4)
Warning: Target library contains no replacement for register 'timer_2_reset_reg' (**FFGEN**). (TRANS-4)
Updating timing information
Information: Updating design information... (UID-85)
Information: Design 'controller' has no optimization constraints set. (OPT-108)
Warning: Target library contains no replacement for register 'timer_2_reset_reg' (**FFGEN**). (TRANS-4)
Warning: Target library contains no replacement for register 'timer_1_reset_reg' (**FFGEN**). (TRANS-4)
Warning: Target library contains no replacement for register 'lut_y_reg[0]' (**FFGEN**). (TRANS-4)
Warning: Target library contains no replacement for register 'new_y_reg[0]' (**FFGEN**). (TRANS-4)
Warning: Target library contains no replacement for register 'lut_y_reg[3]' (**FFGEN**). (TRANS-4)
Warning: Target library contains no replacement for register 'cur_y_reg[3]' (**FFGEN**). (TRANS-4)
Warning: Target library contains no replacement for register 'new_y_reg[3]' (**FFGEN**). (TRANS-4)
Warning: Target library contains no replacement for register 'lut_y_reg[2]' (**FFGEN**). (TRANS-4)
Warning: Target library contains no replacement for register 'cur_y_reg[2]' (**FFGEN**). (TRANS-4)
Warning: Target library contains no replacement for register 'new_y_reg[2]' (**FFGEN**). (TRANS-4)
Warning: Target library contains no replacement for register 'lut_y_reg[1]' (**FFGEN**). (TRANS-4)
Warning: Target library contains no replacement for register 'cur_y_reg[1]' (**FFGEN**). (TRANS-4)
Warning: Target library contains no replacement for register 'new_y_reg[1]' (**FFGEN**). (TRANS-4)
Warning: Target library contains no replacement for register 'cur_y_reg[0]' (**FFGEN**). (TRANS-4)
Warning: Target library contains no replacement for register 'lut_x_reg[0]' (**FFGEN**). (TRANS-4)
Warning: Target library contains no replacement for register 'lut_x_reg[1]' (**FFGEN**). (TRANS-4)
Warning: Target library contains no replacement for register 'lut_piece_type_reg[2]' (**FFGEN**). (TRANS-4)
Warning: Target library contains no replacement for register 'lut_piece_type_reg[1]' (**FFGEN**). (TRANS-4)
Warning: Target library contains no replacement for register 'lut_piece_type_reg[0]' (**FFGEN**). (TRANS-4)
Warning: Target library contains no replacement for register 'lut_start_reg' (**FFGEN**). (TRANS-4)
Warning: Target library contains no replacement for register 'draw_erase_start_reg' (**FFGEN**). (TRANS-4)
Warning: Target library contains no replacement for register 'timer_1_start_reg' (**FFGEN**). (TRANS-4)
Warning: Target library contains no replacement for register 'timer_1_time_reg[2]' (**FFGEN**). (TRANS-4)
Warning: Target library contains no replacement for register 'timer_1_time_reg[3]' (**FFGEN**). (TRANS-4)
Warning: Target library contains no replacement for register 'timer_1_time_reg[4]' (**FFGEN**). (TRANS-4)
Warning: Target library contains no replacement for register 'timer_1_time_reg[5]' (**FFGEN**). (TRANS-4)
Warning: Target library contains no replacement for register 'cur_piece_reg[0]' (**FFGEN**). (TRANS-4)
Warning: Target library contains no replacement for register 'cur_piece_reg[1]' (**FFGEN**). (TRANS-4)
Warning: Target library contains no replacement for register 'cur_piece_reg[2]' (**FFGEN**). (TRANS-4)
Warning: Target library contains no replacement for register 'new_piece_reg' (**FFGEN**). (TRANS-4)
Warning: Target library contains no replacement for register 'clear_shift_start_reg' (**FFGEN**). (TRANS-4)
Warning: Target library contains no replacement for register 'timer_2_time_reg[2]' (**FFGEN**). (TRANS-4)
Warning: Target library contains no replacement for register 'timer_2_time_reg[3]' (**FFGEN**). (TRANS-4)
Warning: Target library contains no replacement for register 'timer_2_time_reg[4]' (**FFGEN**). (TRANS-4)
Warning: Target library contains no replacement for register 'timer_2_time_reg[5]' (**FFGEN**). (TRANS-4)
Warning: Target library contains no replacement for register 'check_start_reg' (**FFGEN**). (TRANS-4)
Warning: Target library contains no replacement for register 'draw_erase_draw_reg' (**FFGEN**). (TRANS-4)
Warning: Target library contains no replacement for register 'timer_2_start_reg' (**FFGEN**). (TRANS-4)
Warning: Target library contains no replacement for register 'next_state_reg[2]' (**FFGEN**). (TRANS-4)
Warning: Target library contains no replacement for register 'next_state_reg[4]' (**FFGEN**). (TRANS-4)
Warning: Target library contains no replacement for register 'next_state_reg[5]' (**FFGEN**). (TRANS-4)
Warning: Target library contains no replacement for register 'next_state_reg[3]' (**FFGEN**). (TRANS-4)
Warning: Target library contains no replacement for register 'next_state_reg[1]' (**FFGEN**). (TRANS-4)
Warning: Target library contains no replacement for register 'next_state_reg[0]' (**FFGEN**). (TRANS-4)
Beginning Mapping Optimizations (Medium effort)
-------------------------------
Structuring 'controller'
Mapping 'controller'
ELAPSED WORST NEG TOTAL NEG DESIGN
TIME AREA SLACK SLACK RULE COST ENDPOINT
--------- --------- --------- --------- --------- -------------------------
0:00:01 993.0 0.00 0.0 12.0
0:00:01 993.0 0.00 0.0 12.0
0:00:01 993.0 0.00 0.0 12.0
0:00:01 993.0 0.00 0.0 12.0
0:00:01 993.0 0.00 0.0 12.0
0:00:01 993.0 0.00 0.0 12.0
0:00:01 993.0 0.00 0.0 12.0
0:00:01 993.0 0.00 0.0 12.0
0:00:01 993.0 0.00 0.0 12.0
0:00:01 993.0 0.00 0.0 12.0
0:00:01 1002.0 0.00 0.0 2.3
0:00:01 1004.0 0.00 0.0 1.2
0:00:01 1006.0 0.00 0.0 0.0
0:00:01 1006.0 0.00 0.0 0.0
0:00:01 1006.0 0.00 0.0 0.0
0:00:01 1006.0 0.00 0.0 0.0
0:00:01 1006.0 0.00 0.0 0.0
Beginning Delay Optimization Phase
----------------------------------
ELAPSED WORST NEG TOTAL NEG DESIGN
TIME AREA SLACK SLACK RULE COST ENDPOINT
--------- --------- --------- --------- --------- -------------------------
0:00:01 1006.0 0.00 0.0 0.0
0:00:01 1006.0 0.00 0.0 0.0
0:00:01 1006.0 0.00 0.0 0.0
Beginning Area-Recovery Phase (cleanup)
-----------------------------
ELAPSED WORST NEG TOTAL NEG DESIGN
TIME AREA SLACK SLACK RULE COST ENDPOINT
--------- --------- --------- --------- --------- -------------------------
0:00:01 1006.0 0.00 0.0 0.0
0:00:01 1006.0 0.00 0.0 0.0
0:00:01 1006.0 0.00 0.0 0.0
0:00:01 994.0 0.00 0.0 0.0
0:00:01 994.0 0.00 0.0 0.0
0:00:01 994.0 0.00 0.0 0.0
0:00:01 994.0 0.00 0.0 0.0
0:00:01 994.0 0.00 0.0 0.0
0:00:01 994.0 0.00 0.0 0.0
0:00:01 994.0 0.00 0.0 0.0
0:00:01 994.0 0.00 0.0 0.0
0:00:01 994.0 0.00 0.0 0.0
0:00:01 994.0 0.00 0.0 0.0
0:00:01 994.0 0.00 0.0 0.0
0:00:01 994.0 0.00 0.0 0.0
0:00:01 994.0 0.00 0.0 0.0
Loading db file '/data/public/common/software/opprog/synth_libs/g_digilib5_99.db'
Loading db file '/data/public/common/software/opprog/synth_libs/buffers.db'
Optimization Complete
---------------------
1
ungroup -all -flat
Warning: Design has no hierarchy. No cells can be ungrouped. (UID-228)
0
report_area
****************************************
Report : area
Design : controller
Version: G-2012.06
Date : Mon Dec 2 20:34:49 2013
****************************************
Information: Updating design information... (UID-85)
Library(s) Used:
g_digilib5_99 (File: /data/public/common/software/opprog/synth_libs/g_digilib5_99.db)
Number of ports: 61
Number of nets: 549
Number of cells: 334
Number of combinational cells: 284
Number of sequential cells: 50
Number of macros: 0
Number of buf/inv: 60
Number of references: 10
Combinational area: 868.000000
Noncombinational area: 126.000000
Net Interconnect area: undefined (No wire load specified)
Total cell area: 994.000000
Total area: undefined
Information: This design contains unmapped logic. (RPT-7)
1
report_fsm
****************************************
Report : FSM
Design : controller
Version: G-2012.06
Date : Mon Dec 2 20:34:49 2013
****************************************
Clock : Unspecified
Asynchronous Reset: Unspecified
Encoding Bit Length: 6
Encoding style : auto
State Vector: { cur_state_reg[5] cur_state_reg[4] cur_state_reg[3] cur_state_reg[2] cur_state_reg[1] cur_state_reg[0] }
State Encodings and Order:
reset : 000000
init : 000001
drop_timer_reset : 000010
gen_piece_1 : 000011
gen_piece_2 : 000100
collision_1 : 000101
collision_2 : 000110
collision_3 : 000111
collision_4 : 001000
collision_5 : 001001
draw : 001010
kernel_panic : 001011
lock_overflow : 001100
reset_timers_a_1 : 001101
reset_timers_a_2 : 001110
clear_shift_1 : 001111
clear_shift_2 : 010000
space_1 : 010001
space_2 : 010010
space_3 : 010011
space_4 : 010100
space_5 : 010101
space_6 : 010110
spaxe_6 : 010111
put_back_1 : 011000
put_back_2 : 011001
put_back_3 : 011010
put_back_4 : 011011
move_down_1 : 011100
move_down_2 : 011101
move_down_3 : 011110
move_down_4 : 011111
reset_timers_b_1 : 100000
reset_timers_b_2 : 100001
drop_timer_reset_1 : 100010
drop_timer_reset_2 : 100011
drop_timer_reset_3 : 100100
drop_overflow : 100101
rotate : 100110
key : 100111
lock_timer_start : 101000
game_over : 101001
1
write_file -f ddc controller -output ./ADB/controller.ddc
Writing ddc file './ADB/controller.ddc'.
1
write_file -f vhdl controller -output ./VHDL/controller_SYNTH.vhd
Writing vhdl file '/home/epo3-user/Desktop/epo3/master/VHDL/controller_SYNTH.vhd'.
Warning: A dummy net 'n_1000' is created to connect open pin 'QN'. (VHDL-290)
Warning: A dummy net 'n_1001' is created to connect open pin 'QN'. (VHDL-290)
Warning: A dummy net 'n_1002' is created to connect open pin 'QN'. (VHDL-290)
Warning: A dummy net 'n_1003' is created to connect open pin 'QN'. (VHDL-290)
Warning: A dummy net 'n_1004' is created to connect open pin 'QN'. (VHDL-290)
Warning: A dummy net 'n_1005' is created to connect open pin 'QN'. (VHDL-290)
Warning: A dummy net 'n_1006' is created to connect open pin 'QN'. (VHDL-290)
Warning: A dummy net 'n_1007' is created to connect open pin 'QN'. (VHDL-290)
Warning: A dummy net 'n_1008' is created to connect open pin 'QN'. (VHDL-290)
Warning: A dummy net 'n_1009' is created to connect open pin 'QN'. (VHDL-290)
Warning: A dummy net 'n_1010' is created to connect open pin 'QN'. (VHDL-290)
Warning: A dummy net 'n_1011' is created to connect open pin 'QN'. (VHDL-290)
Warning: A dummy net 'n_1012' is created to connect open pin 'QN'. (VHDL-290)
Warning: A dummy net 'n_1013' is created to connect open pin 'QN'. (VHDL-290)
Warning: A dummy net 'n_1014' is created to connect open pin 'QN'. (VHDL-290)
Warning: A dummy net 'n_1015' is created to connect open pin 'QN'. (VHDL-290)
Warning: A dummy net 'n_1016' is created to connect open pin 'QN'. (VHDL-290)
Warning: A dummy net 'n_1017' is created to connect open pin 'QN'. (VHDL-290)
Warning: A dummy net 'n_1018' is created to connect open pin 'QN'. (VHDL-290)
Warning: A dummy net 'n_1019' is created to connect open pin 'QN'. (VHDL-290)
Warning: A dummy net 'n_1020' is created to connect open pin 'QN'. (VHDL-290)
Warning: A dummy net 'n_1021' is created to connect open pin 'QN'. (VHDL-290)
Warning: A dummy net 'n_1022' is created to connect open pin 'QN'. (VHDL-290)
Warning: A dummy net 'n_1023' is created to connect open pin 'QN'. (VHDL-290)
Warning: A dummy net 'n_1024' is created to connect open pin 'QN'. (VHDL-290)
Warning: A dummy net 'n_1025' is created to connect open pin 'QN'. (VHDL-290)
Warning: A dummy net 'n_1026' is created to connect open pin 'QN'. (VHDL-290)
Warning: A dummy net 'n_1027' is created to connect open pin 'QN'. (VHDL-290)
Warning: A dummy net 'n_1028' is created to connect open pin 'QN'. (VHDL-290)
Warning: A dummy net 'n_1029' is created to connect open pin 'QN'. (VHDL-290)
Warning: A dummy net 'n_1030' is created to connect open pin 'QN'. (VHDL-290)
Warning: A dummy net 'n_1031' is created to connect open pin 'QN'. (VHDL-290)
Warning: A dummy net 'n_1032' is created to connect open pin 'QN'. (VHDL-290)
Warning: A dummy net 'n_1033' is created to connect open pin 'QN'. (VHDL-290)
Warning: A dummy net 'n_1034' is created to connect open pin 'QN'. (VHDL-290)
Warning: A dummy net 'n_1035' is created to connect open pin 'QN'. (VHDL-290)
Warning: A dummy net 'n_1036' is created to connect open pin 'QN'. (VHDL-290)
Warning: A dummy net 'n_1037' is created to connect open pin 'QN'. (VHDL-290)
1
quit
Thank you...
****** ERRORS found during synthsis *****
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