gistfile1.vhdl

if (rising_edge(clk)) then
    tick_counter := tick_counter + 1;
    if (sensor_mem /= sensor_in and sensor_in = '1') then
        if (measure = 1) then
			if (i < 2) then -- the number of ticks in a frequency will be measured X times
				sum := sum + tick_counter;
				i   := i + 1;
			elsif (i = 2) then
				counter_trigger := sum / 2; -- average ticks 
				sum             := 0;
				measure         := 0;
				i               := 0;
			end if;
		end if;
		tick_counter := 0;
    end if;
    sensor_mem := sensor_in;
end if;