My way to figure out this question on Electrical Engineering StackExchange: http://electronics.stackexchange.com/q/222382/103426

test.vhd

library ieee;
use ieee.std_logic_1164.all;

entity circuit is
  port (
    A, B, C, D: in std_logic;
    F         : out std_logic);
end circuit;

architecture circuit_arc of circuit is
  signal a_not, c_not, ancn_out, anb_out, abd_out: std_logic;
begin
    a_not <= not A after 1 ns;
    c_not <= not C after 1 ns;
    ancn_out <= not (a_not and c_not) after 1 ns;
    anb_out <= not (a_not and B) after 1 ns;
    abd_out <= not (A and B and D) after 1 ns;
    F <= not (ancn_out and anb_out and abd_out);
end circuit_arc;

testbench.vhd

library ieee;
use ieee.std_logic_1164.all;

entity test_bench is
end test_bench;

architecture test_fixture of test_bench is
  component circuit
  port (
    A, B, C, D: in std_logic;
    F         : out std_logic);
  end component;
  signal clk : std_logic := '0';
  signal A,B,C,D,F : std_logic;
begin
  U1: circuit port map (A,B,C,D,F);
  B <= '1';
  C <= '1';
  D <= '1';
  process(clk)
  begin
    A <= clk;
  end process;
  clk <= not clk after 10 ns;
end test_fixture;