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void init_pwm() { | |
// outputs | |
DDRB |= (1 << 2); // PB2 | |
DDRD |= (1 << 5); // PD5 | |
// Waveform Generation Mode to Fast PWM (WGM0[0:2]=7) | |
TCCR0A = (3 << COM0A1) // Set OC0A on Compare Match, clear OC0A at TOP | |
| (3 << COM0B1) // Set OC0B on Compare Match, clear OC0B at TOP | |
| (1 << WGM00) | |
| (1 << WGM01); | |
} | |
#define PWM_CLK_OFF 0 | |
#define PWM_CLK_DIV_1 1 | |
#define PWM_CLK_DIV_8 2 | |
#define PWM_CLK_DIV_64 3 | |
#define PWM_CLK_DIV_256 4 | |
#define PWM_CLK_DIV_1024 5 | |
void set_pwm_clk(uint8_t clk_selector) { | |
TCCR0B = (clk_selector << CS00); | |
} | |
inline void set_pwm_PB2(uint8_t duty) { | |
OCR0A = duty; | |
} | |
inline void set_pwm_PD5(uint8_t duty) { | |
OCR0B = duty; | |
} |
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