ravijain056

from myhdl import block, always_seq, always_comb, Signal, intbv, enum,\
    ResetSignal
from gemac.crc32 import crc32


txstate = enum('IDLE', 'PREAMBLE', 'SFD', 'FIRSTBYTE', 'INFRAME', 'PADDING',
               'ERROR', 'CRC1', 'CRC2', 'CRC3', 'CRC4', 'SENDPAUSE')


@block

ravijain056

from myhdl import block, instance, always_comb, Signal


@block
def orgate(input1, input2, output):
    
    @always_comb
    def orlogic():
        output.next = input1 | input2
        

ravijain056

from myhdl import block, Signal, instance, delay, always, intbv, StopSimulation, modbv
from myhdl.conversion import verify


@block
def top(clk, in1, out1):
    
    index = Signal(modbv(0, min=0, max=8))
    
    @always(clk.posedge)

ravijain056

from myhdl import Signal, block, always_seq, instance, delay


@block
def deadlock():  # not convertible
    sig1 = Signal(bool(0))
    
    @instance
    def initialpush():
        yield delay(10)

ravijain056

from myhdl import Signal, TristateSignal, block, instance, delay, always_comb, always_seq


@block
def foo(clk, iopin):
    
    tri = Signal(bool(0))
    iopindriver = iopin.driver()
    """
    @always_comb

ravijain056

from myhdl import Signal, TristateSignal, block, instance, delay, always_comb


@block
def foo(clk, iopin):
    
    tri = Signal(bool(0))
    iopindriver = iopin.driver()
    
    @always_comb

ravijain056

from myhdl import Signal, instances


class A_Interface:
  def __init__(self):
    a = Signal(bool(0)) 
    
class B_Interface:
  def __init__(self):
    b = Signal(bool(0))

ravijain056

#include <iostream>
using namespace std;

int main() {
    int t;
    cin >> t;
    while(t--) {
        long int cave_size, tractor_size;
        cin >> cave_size >> tractor_size;
        int cave[cave_size][cave_size];

ravijain056

from random import randint
from myhdl import *

def m_2dlos(clock, reset, x, y, Nrows=4, Mcols=8):

    mem2d = [[Signal(intbv(randint(1, 7689), min=0, max=7690)) 
              for col in range(Mcols)] 
             for row in range(Nrows)]
    rcnt = Signal(modbv(0, min=0, max=4))
    ccnt = Signal(modbv(0, min=0, max=8))

ravijain056

from __future__ import absolute_import
import os
path = os.path

from myhdl import *

def ram1(dout, din, addrx, addry, we, clk, depth=128, width=8):
    """ Simple ram model """

    @instance