ravijain056

from myhdl import block, Signal, instance, delay, always, intbv, StopSimulation, modbv
from myhdl.conversion import verify


@block
def top(clk, in1, out1):
    
    index = Signal(modbv(0, min=0, max=8))
    
    @always(clk.posedge)

ravijain056

from myhdl import block, instance, always_comb, Signal


@block
def orgate(input1, input2, output):
    
    @always_comb
    def orlogic():
        output.next = input1 | input2
        

ravijain056

from myhdl import block, always_seq, always_comb, Signal, intbv, enum,\
    ResetSignal
from gemac.crc32 import crc32


txstate = enum('IDLE', 'PREAMBLE', 'SFD', 'FIRSTBYTE', 'INFRAME', 'PADDING',
               'ERROR', 'CRC1', 'CRC2', 'CRC3', 'CRC4', 'SENDPAUSE')


@block