Created
September 11, 2017 19:49
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emacs verilog-mode : connecting all inputs to zero, all outputs floatting
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| /* XXXXXXXX AUTO_TEMPLATE( | |
| .\(.*\) (@"(if (equal vl-dir \\"input\\") (concat vl-width \\"'b0\\") \\"\\" )"), | |
| .\(.*\) (@"(if (equal vl-dir \\"output\\") \\"\\" (concat vl-width \\"'b0\\") )"), | |
| ); */ |
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