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@rbarzic
rbarzic / gist:9cef25062c85442049fdb31607ed24b4
Created March 2, 2020 10:04
Connect input port to 0, left output port floatting emacs auto verilog
// A match is needed for this to work
.fu_\(.*\)_hwdata (@"(if (equal vl-dir \\"output\\") \\"\\" (concat \\"{\\" (concat vl-width \\"{1'b0}}\\")))"),
@rbarzic
rbarzic / gist:59232b080a022417cac434c31152da94
Created January 30, 2019 08:25
Example of org-mode/tangle
#+TITLE: Example of using org/babel to do litterate programming
#+AUTHOR: Ronan BARZIC
#+EMAIL: ronan.barzic@onio.com
To "tangle" it : C-c C-v t
#+BEGIN_SRC python :noweb yes :tangle HelloWorld.py :exports none
"""This is a hello world example document"""
# imports
@rbarzic
rbarzic / gist:b8482e6e76b6fea4e05720cb6e3da5ee
Created January 28, 2019 12:08
riscv custom instruction in inline assembly
From https://groups.google.com/a/groups.riscv.org/d/msg/isa-dev/fONrcF2lxhQ/sb2ZN5Q_AQAJ
rohan:2183$ cat tmp.c
int
sub (int a, int b)
{
int result;
asm (".insn r 0x33, 0, 0, %0, %1, %2" : "=r" (result) : "r" (a), "r" (b));
return result;
}
@rbarzic
rbarzic / gist:cee27283d4a43bec2170d4aeb66a6cb0
Created January 2, 2019 20:22
Perl in-place replacement
perl -p -i -e "s/$(ORIGINAL_STRING)/$(NEW_STRING)/g"
@rbarzic
rbarzic / gist:556f5e5bf104bebc82814abdda9b23c9
Created August 13, 2018 12:28
simple lisp/emacs/verilog-mode
.ahb_bridge_\([a-z0-9]+\)(amlimain_togdr_\1@"vl-bits"),
.bridge_ahb_\([a-z0-9]+\)(togdr_amlimain_\1@"vl-bits"),
@rbarzic
rbarzic / gist:f1b888a75fed44df0583257dc3221c50
Created May 23, 2018 07:14
Autovification in Python using a dedicated class
class AutoVivification(dict):
"""Implementation of perl's autovivification feature."""
def __getitem__(self, item):
try:
return dict.__getitem__(self, item)
except KeyError:
value = self[item] = type(self)()
return value
@rbarzic
rbarzic / gist:3363b5ce48f92e90aae545d850d6813d
Created May 23, 2018 07:13
Autovification in Python using defaultdict
# From https://stackoverflow.com/questions/5369723/multi-level-defaultdict-with-variable-depth/8702435#8702435
from collections import defaultdict
nested_dict = lambda: defaultdict(nested_dict)
nest = nested_dict()
nest[0][1][2][3][4][5] = 6
////////////////////////////////////////
// Bus Interface Unit
// It is assumed that the BIU has internal registers, and will
// latch address, operation, and write data on rising clock edge
// when strobe is asserted
// We implement a glitch filter....
wire biu_clr_err_dly;
wire biu_clr_err_filtered;
@rbarzic
rbarzic / gist:04f2f9bc7d19653a142ba65deb85ad35
Created October 6, 2017 07:46
Makefile uppercase/lower case conversion
ORIGINAL_IP=Nrv32Sig
TARGET_IP=ssctrL
ORIGINAL_IP_LOWER = $(shell echo $(ORIGINAL_IP) | tr '[:upper:]' '[:lower:]')
TARGET_IP_LOWER = $(shell echo $(TARGET_IP) | tr '[:upper:]' '[:lower:]')
ORIGINAL_IP_UPPER = $(shell echo $(ORIGINAL_IP) | tr '[:lower:]' '[:upper:]')
TARGET_IP_UPPER = $(shell echo $(TARGET_IP) | tr '[:lower:]' '[:upper:]')
debug:
@rbarzic
rbarzic / gist:6421d2d8745d24711abd717b92ad1af2
Created September 11, 2017 19:49
emacs verilog-mode : connecting all inputs to zero, all outputs floatting
/* XXXXXXXX AUTO_TEMPLATE(
.\(.*\) (@"(if (equal vl-dir \\"input\\") (concat vl-width \\"'b0\\") \\"\\" )"),
.\(.*\) (@"(if (equal vl-dir \\"output\\") \\"\\" (concat vl-width \\"'b0\\") )"),
); */