Created
March 2, 2020 10:04
-
-
Save rbarzic/9cef25062c85442049fdb31607ed24b4 to your computer and use it in GitHub Desktop.
Connect input port to 0, left output port floatting emacs auto verilog
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
| // A match is needed for this to work | |
| .fu_\(.*\)_hwdata (@"(if (equal vl-dir \\"output\\") \\"\\" (concat \\"{\\" (concat vl-width \\"{1'b0}}\\")))"), |
This is another working example I use for scan pins. All inputs driven to '0 and all outputs open.
.(.scan.) (@"(if (equal vl-dir "input") "'0" "")"),
Here are some examples of using vl-dir. Based on dir the prefix name changes.
.(a.*) (@"(if (equal vl-dir "input") "snoc_ddr_ss_ctgt_\1" "ddr_snoc_ss_ctgt_\1")"),
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
So can be written like if the matching requirement is annoying
.(fu_ahbmatrix_hwdata) (@"(if (equal vl-dir \"output\") \"\" (concat \"{\" (concat vl-width \"{1'b0}}\")))"),