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#include <stdio.h>
#include <stdlib.h>
#include <pthread.h>
//Variables globales
int num_of_threads = 4;
int row = 16,col=16;
double** A;
double** B;
double** C;
# -*- coding: utf-8 -*-
"""
Created on Wed Jul 12 21:54:43 2017
@author: rodolfo
"""
import numpy as np
import threading
# -*- coding: utf-8 -*-
"""
Created on Sat Nov 12 01:40:52 2016
@author: rodolfo
"""
import numpy as np
from sklearn.neighbors import KNeighborsClassifier
data = np.loadtxt('conejos.csv',delimiter=',')
-- -------------------------------------------------------------
--
-- File Name: hdlsrc\Ejemplo_HDL\Ejemplo_HDL.vhd
-- Created: 2017-10-14 23:09:58
--
-- Generated by MATLAB 8.5 and HDL Coder 3.6
--
--
-- -------------------------------------------------------------
-- Rate and Clocking Details
----------------------------------------------------------------------------------
-- COPYRIGHT 2013 Carlos Garcia Lucero
--This program is free software: you can redistribute it and/or modify
--it under the terms of the GNU General Public License as published by
--the Free Software Foundation, either version 3 of the License, or
--(at your option) any later version.
--
--This program is distributed in the hope that it will be useful,
--but WITHOUT ANY WARRANTY; without even the implied warranty of
--MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
----------------------------------------------------------------------------------
-- Company: BUAP
-- Engineer: Rodolfo Emilio Escobar Uribe
--
-- Create Date: 20:42:27 10/15/2017
-- Design Name:
-- Module Name: Control - Behavioral
-- Project Name: Qik 2s12v10 Dual Serial Motor Controller VHDL module
-- Target Devices:
-- Tool versions:
----------------------------------------------------------------------------------
-- Company: BUAP
-- Engineer: Rodolfo Emilio Escobar Uribe
--
-- Create Date: 20:42:27 10/15/2017
-- Design Name:
-- Module Name: Control - Behavioral
-- Project Name: Qik 2s12v10 Dual Serial Motor Controller VHDL module
-- Target Devices:
-- Tool versions:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity encoder is
Port ( Clk : in STD_LOGIC;
A : in STD_LOGIC;
B : in STD_LOGIC;
POS : out STD_LOGIC_VECTOR (15 downto 0));
end encoder;
-- -------------------------------------------------------------
--
-- File Name: hdlsrc\Control_P_Div_HDL\Control_P_Div_HDL.vhd
-- Created: 2017-11-05 22:25:53
--
-- Generated by MATLAB 8.5 and HDL Coder 3.6
--
--
-- -------------------------------------------------------------
-- Rate and Clocking Details
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity fixed_mult is
Port ( ADC : in STD_LOGIC_VECTOR (11 downto 0);
DAC : out STD_LOGIC_VECTOR (11 downto 0));
end fixed_mult;
architecture Behavioral of fixed_mult is