Last active
June 1, 2019 14:53
-
-
Save rowanG077/4aa312608f3b12ef0f113c53b4842d08 to your computer and use it in GitHub Desktop.
de0-nano-soc-uart-working.dts
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
/dts-v1/; | |
/memreserve/ 0x0000000000000000 0x0000000000001000; | |
/ { | |
#address-cells = <0x1>; | |
#size-cells = <0x1>; | |
model = "Terasic DE-0(Atlas)"; | |
compatible = "altr,socfpga-cyclone5", "altr,socfpga"; | |
chosen { | |
bootargs = "earlyprintk"; | |
stdout-path = "serial0:115200n8"; | |
}; | |
aliases { | |
ethernet0 = "/soc/ethernet@ff702000"; | |
ethernet1 = "/soc/ethernet@ff702000"; | |
serial0 = "/soc/serial0@ffc02000"; | |
serial1 = "/soc/serial1@ffc03000"; | |
timer0 = "/soc/timer0@ffc08000"; | |
timer1 = "/soc/timer1@ffc09000"; | |
timer2 = "/soc/timer2@ffd00000"; | |
timer3 = "/soc/timer3@ffd01000"; | |
}; | |
memory { | |
device_type = "memory"; | |
reg = <0x0 0x40000000>; | |
}; | |
cpus { | |
#address-cells = <0x1>; | |
#size-cells = <0x0>; | |
enable-method = "altr,socfpga-smp"; | |
cpu@0 { | |
compatible = "arm,cortex-a9"; | |
device_type = "cpu"; | |
reg = <0x0>; | |
next-level-cache = <0x1>; | |
}; | |
cpu@1 { | |
compatible = "arm,cortex-a9"; | |
device_type = "cpu"; | |
reg = <0x1>; | |
next-level-cache = <0x1>; | |
}; | |
}; | |
intc@fffed000 { | |
compatible = "arm,cortex-a9-gic"; | |
#interrupt-cells = <0x3>; | |
interrupt-controller; | |
reg = <0xfffed000 0x1000 0xfffec100 0x100>; | |
linux,phandle = <0x2>; | |
phandle = <0x2>; | |
}; | |
soc { | |
#address-cells = <0x1>; | |
#size-cells = <0x1>; | |
compatible = "altr,avalon", "simple-bus"; | |
device_type = "soc"; | |
interrupt-parent = <0x2>; | |
ranges; | |
bridge@c0000000 { | |
compatible = "altr,bridge-17.1", "simple-bus"; | |
reg = <0xc0000000 0x20000000>; | |
#address-cells = <2>; | |
#size-cells = <1>; | |
ranges = <0x00000000 0x00004000 0xc0004000 0x00000020>; | |
serial@000004000 { | |
compatible = "altr,uart-17.1", "altr,uart-1.0"; | |
reg = <0x00000000 0x00004000 0x00000020>; | |
interrupt-parent = <2>; | |
interrupts = <0 40 4>; | |
clock-frequency = <50000000>; | |
current-speed = <19200>; | |
}; | |
}; | |
amba { | |
compatible = "simple-bus"; | |
#address-cells = <0x1>; | |
#size-cells = <0x1>; | |
ranges; | |
pdma@ffe01000 { | |
compatible = "arm,pl330", "arm,primecell"; | |
reg = <0xffe01000 0x1000>; | |
interrupts = <0x0 0x68 0x4 0x0 0x69 0x4 0x0 0x6a 0x4 0x0 0x6b 0x4 0x0 0x6c 0x4 0x0 0x6d 0x4 0x0 0x6e 0x4 0x0 0x6f 0x4>; | |
#dma-cells = <0x1>; | |
#dma-channels = <0x8>; | |
#dma-requests = <0x20>; | |
clocks = <0x3>; | |
clock-names = "apb_pclk"; | |
linux,phandle = <0x2b>; | |
phandle = <0x2b>; | |
}; | |
}; | |
can@ffc00000 { | |
compatible = "bosch,d_can"; | |
reg = <0xffc00000 0x1000>; | |
interrupts = <0x0 0x83 0x4 0x0 0x84 0x4 0x0 0x85 0x4 0x0 0x86 0x4>; | |
clocks = <0x4>; | |
status = "disabled"; | |
}; | |
can@ffc01000 { | |
compatible = "bosch,d_can"; | |
reg = <0xffc01000 0x1000>; | |
interrupts = <0x0 0x87 0x4 0x0 0x88 0x4 0x0 0x89 0x4 0x0 0x8a 0x4>; | |
clocks = <0x5>; | |
status = "disabled"; | |
}; | |
clkmgr@ffd04000 { | |
compatible = "altr,clk-mgr"; | |
reg = <0xffd04000 0x1000>; | |
clocks { | |
#address-cells = <0x1>; | |
#size-cells = <0x0>; | |
osc1 { | |
#clock-cells = <0x0>; | |
compatible = "fixed-clock"; | |
clock-frequency = <0x17d7840>; | |
linux,phandle = <0x6>; | |
phandle = <0x6>; | |
}; | |
osc2 { | |
#clock-cells = <0x0>; | |
compatible = "fixed-clock"; | |
linux,phandle = <0x8>; | |
phandle = <0x8>; | |
}; | |
f2s_periph_ref_clk { | |
#clock-cells = <0x0>; | |
compatible = "fixed-clock"; | |
linux,phandle = <0x9>; | |
phandle = <0x9>; | |
}; | |
f2s_sdram_ref_clk { | |
#clock-cells = <0x0>; | |
compatible = "fixed-clock"; | |
linux,phandle = <0xb>; | |
phandle = <0xb>; | |
}; | |
main_pll { | |
#address-cells = <0x1>; | |
#size-cells = <0x0>; | |
#clock-cells = <0x0>; | |
compatible = "altr,socfpga-pll-clock"; | |
clocks = <0x6>; | |
reg = <0x40>; | |
linux,phandle = <0x7>; | |
phandle = <0x7>; | |
mpuclk { | |
#clock-cells = <0x0>; | |
compatible = "altr,socfpga-perip-clk"; | |
clocks = <0x7>; | |
div-reg = <0xe0 0x0 0x9>; | |
reg = <0x48>; | |
linux,phandle = <0xd>; | |
phandle = <0xd>; | |
}; | |
mainclk { | |
#clock-cells = <0x0>; | |
compatible = "altr,socfpga-perip-clk"; | |
clocks = <0x7>; | |
div-reg = <0xe4 0x0 0x9>; | |
reg = <0x4c>; | |
linux,phandle = <0xe>; | |
phandle = <0xe>; | |
}; | |
dbg_base_clk { | |
#clock-cells = <0x0>; | |
compatible = "altr,socfpga-perip-clk"; | |
clocks = <0x7 0x6>; | |
div-reg = <0xe8 0x0 0x9>; | |
reg = <0x50>; | |
linux,phandle = <0x11>; | |
phandle = <0x11>; | |
}; | |
main_qspi_clk { | |
#clock-cells = <0x0>; | |
compatible = "altr,socfpga-perip-clk"; | |
clocks = <0x7>; | |
reg = <0x54>; | |
linux,phandle = <0x1a>; | |
phandle = <0x1a>; | |
}; | |
main_nand_sdmmc_clk { | |
#clock-cells = <0x0>; | |
compatible = "altr,socfpga-perip-clk"; | |
clocks = <0x7>; | |
reg = <0x58>; | |
linux,phandle = <0x17>; | |
phandle = <0x17>; | |
}; | |
cfg_h2f_usr0_clk { | |
#clock-cells = <0x0>; | |
compatible = "altr,socfpga-perip-clk"; | |
clocks = <0x7>; | |
reg = <0x5c>; | |
linux,phandle = <0x13>; | |
phandle = <0x13>; | |
}; | |
}; | |
periph_pll { | |
#address-cells = <0x1>; | |
#size-cells = <0x0>; | |
#clock-cells = <0x0>; | |
compatible = "altr,socfpga-pll-clock"; | |
clocks = <0x6 0x8 0x9>; | |
reg = <0x80>; | |
linux,phandle = <0xa>; | |
phandle = <0xa>; | |
emac0_clk { | |
#clock-cells = <0x0>; | |
compatible = "altr,socfpga-perip-clk"; | |
clocks = <0xa>; | |
reg = <0x88>; | |
linux,phandle = <0x14>; | |
phandle = <0x14>; | |
}; | |
emac1_clk { | |
#clock-cells = <0x0>; | |
compatible = "altr,socfpga-perip-clk"; | |
clocks = <0xa>; | |
reg = <0x8c>; | |
linux,phandle = <0x15>; | |
phandle = <0x15>; | |
}; | |
per_qsi_clk { | |
#clock-cells = <0x0>; | |
compatible = "altr,socfpga-perip-clk"; | |
clocks = <0xa>; | |
reg = <0x90>; | |
linux,phandle = <0x1b>; | |
phandle = <0x1b>; | |
}; | |
per_nand_mmc_clk { | |
#clock-cells = <0x0>; | |
compatible = "altr,socfpga-perip-clk"; | |
clocks = <0xa>; | |
reg = <0x94>; | |
linux,phandle = <0x18>; | |
phandle = <0x18>; | |
}; | |
per_base_clk { | |
#clock-cells = <0x0>; | |
compatible = "altr,socfpga-perip-clk"; | |
clocks = <0xa>; | |
reg = <0x98>; | |
linux,phandle = <0x10>; | |
phandle = <0x10>; | |
}; | |
h2f_usr1_clk { | |
#clock-cells = <0x0>; | |
compatible = "altr,socfpga-perip-clk"; | |
clocks = <0xa>; | |
reg = <0x9c>; | |
linux,phandle = <0x16>; | |
phandle = <0x16>; | |
}; | |
}; | |
sdram_pll { | |
#address-cells = <0x1>; | |
#size-cells = <0x0>; | |
#clock-cells = <0x0>; | |
compatible = "altr,socfpga-pll-clock"; | |
clocks = <0x6 0x8 0xb>; | |
reg = <0xc0>; | |
linux,phandle = <0xc>; | |
phandle = <0xc>; | |
ddr_dqs_clk { | |
#clock-cells = <0x0>; | |
compatible = "altr,socfpga-perip-clk"; | |
clocks = <0xc>; | |
reg = <0xc8>; | |
linux,phandle = <0x1c>; | |
phandle = <0x1c>; | |
}; | |
ddr_2x_dqs_clk { | |
#clock-cells = <0x0>; | |
compatible = "altr,socfpga-perip-clk"; | |
clocks = <0xc>; | |
reg = <0xcc>; | |
linux,phandle = <0x1d>; | |
phandle = <0x1d>; | |
}; | |
ddr_dq_clk { | |
#clock-cells = <0x0>; | |
compatible = "altr,socfpga-perip-clk"; | |
clocks = <0xc>; | |
reg = <0xd0>; | |
linux,phandle = <0x1e>; | |
phandle = <0x1e>; | |
}; | |
h2f_usr2_clk { | |
#clock-cells = <0x0>; | |
compatible = "altr,socfpga-perip-clk"; | |
clocks = <0xc>; | |
reg = <0xd4>; | |
linux,phandle = <0x1f>; | |
phandle = <0x1f>; | |
}; | |
}; | |
mpu_periph_clk { | |
#clock-cells = <0x0>; | |
compatible = "altr,socfpga-perip-clk"; | |
clocks = <0xd>; | |
fixed-divider = <0x4>; | |
linux,phandle = <0x2a>; | |
phandle = <0x2a>; | |
}; | |
mpu_l2_ram_clk { | |
#clock-cells = <0x0>; | |
compatible = "altr,socfpga-perip-clk"; | |
clocks = <0xd>; | |
fixed-divider = <0x2>; | |
}; | |
l4_main_clk { | |
#clock-cells = <0x0>; | |
compatible = "altr,socfpga-gate-clk"; | |
clocks = <0xe>; | |
clk-gate = <0x60 0x0>; | |
linux,phandle = <0x3>; | |
phandle = <0x3>; | |
}; | |
l3_main_clk { | |
#clock-cells = <0x0>; | |
compatible = "altr,socfpga-perip-clk"; | |
clocks = <0xe>; | |
fixed-divider = <0x1>; | |
}; | |
l3_mp_clk { | |
#clock-cells = <0x0>; | |
compatible = "altr,socfpga-gate-clk"; | |
clocks = <0xe>; | |
div-reg = <0x64 0x0 0x2>; | |
clk-gate = <0x60 0x1>; | |
linux,phandle = <0xf>; | |
phandle = <0xf>; | |
}; | |
l3_sp_clk { | |
#clock-cells = <0x0>; | |
compatible = "altr,socfpga-gate-clk"; | |
clocks = <0xf>; | |
div-reg = <0x64 0x2 0x2>; | |
}; | |
l4_mp_clk { | |
#clock-cells = <0x0>; | |
compatible = "altr,socfpga-gate-clk"; | |
clocks = <0xe 0x10>; | |
div-reg = <0x64 0x4 0x3>; | |
clk-gate = <0x60 0x2>; | |
linux,phandle = <0x22>; | |
phandle = <0x22>; | |
}; | |
l4_sp_clk { | |
#clock-cells = <0x0>; | |
compatible = "altr,socfpga-gate-clk"; | |
clocks = <0xe 0x10>; | |
div-reg = <0x64 0x7 0x3>; | |
clk-gate = <0x60 0x3>; | |
linux,phandle = <0x23>; | |
phandle = <0x23>; | |
}; | |
dbg_at_clk { | |
#clock-cells = <0x0>; | |
compatible = "altr,socfpga-gate-clk"; | |
clocks = <0x11>; | |
div-reg = <0x68 0x0 0x2>; | |
clk-gate = <0x60 0x4>; | |
linux,phandle = <0x12>; | |
phandle = <0x12>; | |
}; | |
dbg_clk { | |
#clock-cells = <0x0>; | |
compatible = "altr,socfpga-gate-clk"; | |
clocks = <0x12>; | |
div-reg = <0x68 0x2 0x2>; | |
clk-gate = <0x60 0x5>; | |
}; | |
dbg_trace_clk { | |
#clock-cells = <0x0>; | |
compatible = "altr,socfpga-gate-clk"; | |
clocks = <0x11>; | |
div-reg = <0x6c 0x0 0x3>; | |
clk-gate = <0x60 0x6>; | |
}; | |
dbg_timer_clk { | |
#clock-cells = <0x0>; | |
compatible = "altr,socfpga-gate-clk"; | |
clocks = <0x11>; | |
clk-gate = <0x60 0x7>; | |
}; | |
cfg_clk { | |
#clock-cells = <0x0>; | |
compatible = "altr,socfpga-gate-clk"; | |
clocks = <0x13>; | |
clk-gate = <0x60 0x8>; | |
}; | |
h2f_user0_clk { | |
#clock-cells = <0x0>; | |
compatible = "altr,socfpga-gate-clk"; | |
clocks = <0x13>; | |
clk-gate = <0x60 0x9>; | |
}; | |
emac_0_clk { | |
#clock-cells = <0x0>; | |
compatible = "altr,socfpga-gate-clk"; | |
clocks = <0x14>; | |
clk-gate = <0xa0 0x0>; | |
}; | |
emac_1_clk { | |
#clock-cells = <0x0>; | |
compatible = "altr,socfpga-gate-clk"; | |
clocks = <0x15>; | |
clk-gate = <0xa0 0x1>; | |
}; | |
usb_mp_clk { | |
#clock-cells = <0x0>; | |
compatible = "altr,socfpga-gate-clk"; | |
clocks = <0x10>; | |
clk-gate = <0xa0 0x2>; | |
div-reg = <0xa4 0x0 0x3>; | |
linux,phandle = <0x2c>; | |
phandle = <0x2c>; | |
}; | |
spi_m_clk { | |
#clock-cells = <0x0>; | |
compatible = "altr,socfpga-gate-clk"; | |
clocks = <0x10>; | |
clk-gate = <0xa0 0x3>; | |
div-reg = <0xa4 0x3 0x3>; | |
linux,phandle = <0x29>; | |
phandle = <0x29>; | |
}; | |
can0_clk { | |
#clock-cells = <0x0>; | |
compatible = "altr,socfpga-gate-clk"; | |
clocks = <0x10>; | |
clk-gate = <0xa0 0x4>; | |
div-reg = <0xa4 0x6 0x3>; | |
linux,phandle = <0x4>; | |
phandle = <0x4>; | |
}; | |
can1_clk { | |
#clock-cells = <0x0>; | |
compatible = "altr,socfpga-gate-clk"; | |
clocks = <0x10>; | |
clk-gate = <0xa0 0x5>; | |
div-reg = <0xa4 0x9 0x3>; | |
linux,phandle = <0x5>; | |
phandle = <0x5>; | |
}; | |
gpio_db_clk { | |
#clock-cells = <0x0>; | |
compatible = "altr,socfpga-gate-clk"; | |
clocks = <0x10>; | |
clk-gate = <0xa0 0x6>; | |
div-reg = <0xa8 0x0 0x18>; | |
}; | |
h2f_user1_clk { | |
#clock-cells = <0x0>; | |
compatible = "altr,socfpga-gate-clk"; | |
clocks = <0x16>; | |
clk-gate = <0xa0 0x7>; | |
}; | |
sdmmc_clk { | |
#clock-cells = <0x0>; | |
compatible = "altr,socfpga-gate-clk"; | |
clocks = <0x9 0x17 0x18>; | |
clk-gate = <0xa0 0x8>; | |
clk-phase = <0x0 0x87>; | |
linux,phandle = <0x19>; | |
phandle = <0x19>; | |
}; | |
sdmmc_clk_divided { | |
#clock-cells = <0x0>; | |
compatible = "altr,socfpga-gate-clk"; | |
clocks = <0x19>; | |
clk-gate = <0xa0 0x8>; | |
fixed-divider = <0x4>; | |
linux,phandle = <0x26>; | |
phandle = <0x26>; | |
}; | |
nand_x_clk { | |
#clock-cells = <0x0>; | |
compatible = "altr,socfpga-gate-clk"; | |
clocks = <0x9 0x17 0x18>; | |
clk-gate = <0xa0 0x9>; | |
}; | |
nand_clk { | |
#clock-cells = <0x0>; | |
compatible = "altr,socfpga-gate-clk"; | |
clocks = <0x9 0x17 0x18>; | |
clk-gate = <0xa0 0xa>; | |
fixed-divider = <0x4>; | |
}; | |
qspi_clk { | |
#clock-cells = <0x0>; | |
compatible = "altr,socfpga-gate-clk"; | |
clocks = <0x9 0x1a 0x1b>; | |
clk-gate = <0xa0 0xb>; | |
}; | |
ddr_dqs_clk_gate { | |
#clock-cells = <0x0>; | |
compatible = "altr,socfpga-gate-clk"; | |
clocks = <0x1c>; | |
clk-gate = <0xd8 0x0>; | |
}; | |
ddr_2x_dqs_clk_gate { | |
#clock-cells = <0x0>; | |
compatible = "altr,socfpga-gate-clk"; | |
clocks = <0x1d>; | |
clk-gate = <0xd8 0x1>; | |
}; | |
ddr_dq_clk_gate { | |
#clock-cells = <0x0>; | |
compatible = "altr,socfpga-gate-clk"; | |
clocks = <0x1e>; | |
clk-gate = <0xd8 0x2>; | |
}; | |
h2f_user2_clk { | |
#clock-cells = <0x0>; | |
compatible = "altr,socfpga-gate-clk"; | |
clocks = <0x1f>; | |
clk-gate = <0xd8 0x3>; | |
}; | |
}; | |
}; | |
fpgamgr@ff706000 { | |
compatible = "altr,socfpga-fpga-mgr"; | |
reg = <0xff706000 0x1000 0xffb90000 0x1000>; | |
interrupts = <0x0 0xaf 0x4>; | |
}; | |
ethernet@ff700000 { | |
compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac"; | |
altr,sysmgr-syscon = <0x20 0x60 0x0>; | |
reg = <0xff700000 0x2000>; | |
interrupts = <0x0 0x73 0x4>; | |
interrupt-names = "macirq"; | |
mac-address = [00 00 00 00 00 00]; | |
clocks = <0x14>; | |
clock-names = "stmmaceth"; | |
resets = <0x21 0x20>; | |
reset-names = "stmmaceth"; | |
snps,multicast-filter-bins = <0x100>; | |
snps,perfect-filter-entries = <0x80>; | |
tx-fifo-depth = <0x1000>; | |
rx-fifo-depth = <0x1000>; | |
status = "disabled"; | |
}; | |
ethernet@ff702000 { | |
compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac"; | |
altr,sysmgr-syscon = <0x20 0x60 0x2>; | |
reg = <0xff702000 0x2000>; | |
interrupts = <0x0 0x78 0x4>; | |
interrupt-names = "macirq"; | |
mac-address = [00 00 00 00 00 00]; | |
clocks = <0x15>; | |
clock-names = "stmmaceth"; | |
resets = <0x21 0x21>; | |
reset-names = "stmmaceth"; | |
snps,multicast-filter-bins = <0x100>; | |
snps,perfect-filter-entries = <0x80>; | |
tx-fifo-depth = <0x1000>; | |
rx-fifo-depth = <0x1000>; | |
status = "okay"; | |
phy-mode = "rgmii"; | |
txd0-skew-ps = <0x0>; | |
txd1-skew-ps = <0x0>; | |
txd2-skew-ps = <0x0>; | |
txd3-skew-ps = <0x0>; | |
rxd0-skew-ps = <0x1a4>; | |
rxd1-skew-ps = <0x1a4>; | |
rxd2-skew-ps = <0x1a4>; | |
rxd3-skew-ps = <0x1a4>; | |
txen-skew-ps = <0x0>; | |
txc-skew-ps = <0x744>; | |
rxdv-skew-ps = <0x1a4>; | |
rxc-skew-ps = <0x690>; | |
max-frame-size = <0xed8>; | |
}; | |
gpio@ff708000 { | |
#address-cells = <0x1>; | |
#size-cells = <0x0>; | |
compatible = "snps,dw-apb-gpio"; | |
reg = <0xff708000 0x1000>; | |
clocks = <0x22>; | |
status = "okay"; | |
gpio-controller@0 { | |
compatible = "snps,dw-apb-gpio-port"; | |
gpio-controller; | |
#gpio-cells = <0x2>; | |
snps,nr-gpios = <0x1d>; | |
reg = <0x0>; | |
interrupt-controller; | |
#interrupt-cells = <0x2>; | |
interrupts = <0x0 0xa4 0x4>; | |
}; | |
}; | |
gpio@ff709000 { | |
#address-cells = <0x1>; | |
#size-cells = <0x0>; | |
compatible = "snps,dw-apb-gpio"; | |
reg = <0xff709000 0x1000>; | |
clocks = <0x22>; | |
status = "okay"; | |
gpio-controller@0 { | |
compatible = "snps,dw-apb-gpio-port"; | |
gpio-controller; | |
#gpio-cells = <0x2>; | |
snps,nr-gpios = <0x1d>; | |
reg = <0x0>; | |
interrupt-controller; | |
#interrupt-cells = <0x2>; | |
interrupts = <0x0 0xa5 0x4>; | |
linux,phandle = <0x2e>; | |
phandle = <0x2e>; | |
}; | |
}; | |
gpio@ff70a000 { | |
#address-cells = <0x1>; | |
#size-cells = <0x0>; | |
compatible = "snps,dw-apb-gpio"; | |
reg = <0xff70a000 0x1000>; | |
clocks = <0x22>; | |
status = "okay"; | |
gpio-controller@0 { | |
compatible = "snps,dw-apb-gpio-port"; | |
gpio-controller; | |
#gpio-cells = <0x2>; | |
snps,nr-gpios = <0x1b>; | |
reg = <0x0>; | |
interrupt-controller; | |
#interrupt-cells = <0x2>; | |
interrupts = <0x0 0xa6 0x4>; | |
linux,phandle = <0x24>; | |
phandle = <0x24>; | |
}; | |
}; | |
i2c@ffc04000 { | |
#address-cells = <0x1>; | |
#size-cells = <0x0>; | |
compatible = "snps,designware-i2c"; | |
reg = <0xffc04000 0x1000>; | |
clocks = <0x23>; | |
interrupts = <0x0 0x9e 0x4>; | |
status = "okay"; | |
speed-mode = <0x0>; | |
adxl345@0 { | |
compatible = "adi,adxl345"; | |
reg = <0x53>; | |
interrupt-parent = <0x24>; | |
interrupts = <0x3 0x2>; | |
}; | |
}; | |
i2c@ffc05000 { | |
#address-cells = <0x1>; | |
#size-cells = <0x0>; | |
compatible = "snps,designware-i2c"; | |
reg = <0xffc05000 0x1000>; | |
clocks = <0x23>; | |
interrupts = <0x0 0x9f 0x4>; | |
status = "okay"; | |
speed-mode = <0x0>; | |
}; | |
i2c@ffc06000 { | |
#address-cells = <0x1>; | |
#size-cells = <0x0>; | |
compatible = "snps,designware-i2c"; | |
reg = <0xffc06000 0x1000>; | |
clocks = <0x23>; | |
interrupts = <0x0 0xa0 0x4>; | |
status = "disabled"; | |
}; | |
i2c@ffc07000 { | |
#address-cells = <0x1>; | |
#size-cells = <0x0>; | |
compatible = "snps,designware-i2c"; | |
reg = <0xffc07000 0x1000>; | |
clocks = <0x23>; | |
interrupts = <0x0 0xa1 0x4>; | |
status = "disabled"; | |
}; | |
eccmgr@ffd08140 { | |
compatible = "altr,socfpga-ecc-manager"; | |
#address-cells = <0x1>; | |
#size-cells = <0x1>; | |
ranges; | |
l2-ecc@ffd08140 { | |
compatible = "altr,socfpga-l2-ecc"; | |
reg = <0xffd08140 0x4>; | |
interrupts = <0x0 0x24 0x1 0x0 0x25 0x1>; | |
}; | |
ocram-ecc@ffd08144 { | |
compatible = "altr,socfpga-ocram-ecc"; | |
reg = <0xffd08144 0x4>; | |
iram = <0x25>; | |
interrupts = <0x0 0xb2 0x1 0x0 0xb3 0x1>; | |
}; | |
}; | |
l2-cache@fffef000 { | |
compatible = "arm,pl310-cache"; | |
reg = <0xfffef000 0x1000>; | |
interrupts = <0x0 0x26 0x4>; | |
cache-unified; | |
cache-level = <0x2>; | |
arm,tag-latency = <0x1 0x1 0x1>; | |
arm,data-latency = <0x2 0x1 0x1>; | |
prefetch-data = <0x1>; | |
prefetch-instr = <0x1>; | |
linux,phandle = <0x1>; | |
phandle = <0x1>; | |
}; | |
dwmmc0@ff704000 { | |
compatible = "altr,socfpga-dw-mshc"; | |
reg = <0xff704000 0x1000>; | |
interrupts = <0x0 0x8b 0x4>; | |
fifo-depth = <0x400>; | |
#address-cells = <0x1>; | |
#size-cells = <0x0>; | |
clocks = <0x22 0x26>; | |
clock-names = "biu", "ciu"; | |
status = "okay"; | |
num-slots = <0x1>; | |
broken-cd; | |
bus-width = <0x4>; | |
cap-mmc-highspeed; | |
cap-sd-highspeed; | |
vmmc-supply = <0x27>; | |
vqmmc-supply = <0x27>; | |
}; | |
sram@ffff0000 { | |
compatible = "mmio-sram"; | |
reg = <0xffff0000 0x10000>; | |
linux,phandle = <0x25>; | |
phandle = <0x25>; | |
}; | |
rstmgr@ffd05000 { | |
#reset-cells = <0x1>; | |
compatible = "altr,rst-mgr"; | |
reg = <0xffd05000 0x1000>; | |
altr,modrst-offset = <0x10>; | |
linux,phandle = <0x21>; | |
phandle = <0x21>; | |
}; | |
snoop-control-unit@fffec000 { | |
compatible = "arm,cortex-a9-scu"; | |
reg = <0xfffec000 0x100>; | |
}; | |
sdr@ffc25000 { | |
compatible = "syscon"; | |
reg = <0xffc25000 0x1000>; | |
linux,phandle = <0x28>; | |
phandle = <0x28>; | |
}; | |
sdramedac { | |
compatible = "altr,sdram-edac"; | |
altr,sdr-syscon = <0x28>; | |
interrupts = <0x0 0x27 0x4>; | |
}; | |
spi@fff00000 { | |
compatible = "snps,dw-apb-ssi"; | |
#address-cells = <0x1>; | |
#size-cells = <0x0>; | |
reg = <0xfff00000 0x1000>; | |
interrupts = <0x0 0x9a 0x4>; | |
num-cs = <0x4>; | |
clocks = <0x29>; | |
status = "disabled"; | |
}; | |
spi@fff01000 { | |
compatible = "snps,dw-apb-ssi"; | |
#address-cells = <0x1>; | |
#size-cells = <0x0>; | |
reg = <0xfff01000 0x1000>; | |
interrupts = <0x0 0x9b 0x4>; | |
num-cs = <0x4>; | |
clocks = <0x29>; | |
status = "disabled"; | |
}; | |
sysmgr@ffd08000 { | |
compatible = "altr,sys-mgr", "syscon"; | |
reg = <0xffd08000 0x4000>; | |
cpu1-start-addr = <0xffd080c4>; | |
linux,phandle = <0x20>; | |
phandle = <0x20>; | |
}; | |
timer@fffec600 { | |
compatible = "arm,cortex-a9-twd-timer"; | |
reg = <0xfffec600 0x100>; | |
interrupts = <0x1 0xd 0xf01>; | |
clocks = <0x2a>; | |
}; | |
timer0@ffc08000 { | |
compatible = "snps,dw-apb-timer"; | |
interrupts = <0x0 0xa7 0x4>; | |
reg = <0xffc08000 0x1000>; | |
clocks = <0x23>; | |
clock-names = "timer"; | |
}; | |
timer1@ffc09000 { | |
compatible = "snps,dw-apb-timer"; | |
interrupts = <0x0 0xa8 0x4>; | |
reg = <0xffc09000 0x1000>; | |
clocks = <0x23>; | |
clock-names = "timer"; | |
}; | |
timer2@ffd00000 { | |
compatible = "snps,dw-apb-timer"; | |
interrupts = <0x0 0xa9 0x4>; | |
reg = <0xffd00000 0x1000>; | |
clocks = <0x6>; | |
clock-names = "timer"; | |
}; | |
timer3@ffd01000 { | |
compatible = "snps,dw-apb-timer"; | |
interrupts = <0x0 0xaa 0x4>; | |
reg = <0xffd01000 0x1000>; | |
clocks = <0x6>; | |
clock-names = "timer"; | |
}; | |
serial0@ffc02000 { | |
compatible = "snps,dw-apb-uart"; | |
reg = <0xffc02000 0x1000>; | |
interrupts = <0x0 0xa2 0x4>; | |
reg-shift = <0x2>; | |
reg-io-width = <0x4>; | |
clocks = <0x23>; | |
dmas = <0x2b 0x1c 0x2b 0x1d>; | |
dma-names = "tx", "rx"; | |
status = "okay"; | |
}; | |
serial1@ffc03000 { | |
compatible = "snps,dw-apb-uart"; | |
reg = <0xffc03000 0x1000>; | |
interrupts = <0x0 0xa3 0x4>; | |
reg-shift = <0x2>; | |
reg-io-width = <0x4>; | |
clocks = <0x23>; | |
dmas = <0x2b 0x1e 0x2b 0x1f>; | |
dma-names = "tx", "rx"; | |
}; | |
usbphy@0 { | |
#phy-cells = <0x0>; | |
compatible = "usb-nop-xceiv"; | |
status = "okay"; | |
linux,phandle = <0x2d>; | |
phandle = <0x2d>; | |
}; | |
usb@ffb00000 { | |
compatible = "snps,dwc2"; | |
reg = <0xffb00000 0xffff>; | |
interrupts = <0x0 0x7d 0x4>; | |
clocks = <0x2c>; | |
clock-names = "otg"; | |
resets = <0x21 0x22>; | |
reset-names = "dwc2"; | |
phys = <0x2d>; | |
phy-names = "usb2-phy"; | |
status = "okay"; | |
}; | |
usb@ffb40000 { | |
compatible = "snps,dwc2"; | |
reg = <0xffb40000 0xffff>; | |
interrupts = <0x0 0x80 0x4>; | |
clocks = <0x2c>; | |
clock-names = "otg"; | |
resets = <0x21 0x23>; | |
reset-names = "dwc2"; | |
status = "okay"; | |
dr_mode = "host"; | |
}; | |
watchdog@ffd02000 { | |
compatible = "snps,dw-wdt"; | |
reg = <0xffd02000 0x1000>; | |
interrupts = <0x0 0xab 0x4>; | |
clocks = <0x6>; | |
status = "okay"; | |
}; | |
watchdog@ffd03000 { | |
compatible = "snps,dw-wdt"; | |
reg = <0xffd03000 0x1000>; | |
interrupts = <0x0 0xac 0x4>; | |
clocks = <0x6>; | |
status = "disabled"; | |
}; | |
}; | |
3-3-v-regulator { | |
compatible = "regulator-fixed"; | |
regulator-name = "3.3V"; | |
regulator-min-microvolt = <0x325aa0>; | |
regulator-max-microvolt = <0x325aa0>; | |
linux,phandle = <0x27>; | |
phandle = <0x27>; | |
}; | |
leds { | |
compatible = "gpio-leds"; | |
hps0 { | |
label = "hps_led0"; | |
gpios = <0x2e 0x18 0x0>; | |
linux,default-trigger = "heartbeat"; | |
}; | |
}; | |
}; |
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment