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rowanG077 / Main.hs
Last active December 14, 2023 11:06
Clash type level config of primitive
{-# LANGUAGE UndecidableInstances #-}
{-# LANGUAGE MagicHash #-}
{-# LANGUAGE BangPatterns #-}
{-# LANGUAGE AllowAmbiguousTypes #-}
import Clash.Explicit.Prelude
import Clash.Annotations.Primitive
import GHC.TypeLits.KnownNat (KnownBool, boolVal)
import Data.Proxy (Proxy(..))
import Data.Maybe (isJust)
@rowanG077
rowanG077 / dmesg-bootlog-no-hub.txt
Last active February 26, 2023 23:30
OWC TB 4 Hub lspci
[ 0.000000] Linux version 5.15.85 (nixbld@localhost) (gcc (GCC) 11.3.0, GNU ld (GNU Binutils) 2.39) #1-NixOS SMP Wed Dec 21 16:36:38 UTC 2022
[ 0.000000] Command line: initrd=\efi\nixos\j4181djg7k4ikw06z7740zlq6b0p9h5s-initrd-linux-5.15.85-initrd.efi init=/nix/store/5d4j8cc84q0cshq79j6gz67b2f7075s1-nixos-system-rowanG-nixos-23.05pre438362.e182da8622a/init memmap=14M$18M msr.allow_writes=on nopat i915.enable_psr=0 i915.enable_fbc=0 i915.perf_stream_paranoid=0 loglevel=4
[ 0.000000] x86/split lock detection: #AC: crashing the kernel on kernel split_locks and warning on user-space split_locks
[ 0.000000] x86/fpu: Supporting XSAVE feature 0x001: 'x87 floating point registers'
[ 0.000000] x86/fpu: Supporting XSAVE feature 0x002: 'SSE registers'
[ 0.000000] x86/fpu: Supporting XSAVE feature 0x004: 'AVX registers'
[ 0.000000] x86/fpu: Supporting XSAVE feature 0x020: 'AVX-512 opmask'
[ 0.000000] x86/fpu: Supporting XSAVE feature 0x040: 'AVX-512 Hi256'
[ 0.000000] x86/fpu: Supporting XSAVE f
@rowanG077
rowanG077 / open3d.nix
Created July 8, 2021 16:38
{ stdenv, lib, buildPythonPackage, fetchPypi, scipy, scikitlearn, numpy
, matplotlib, ipywidgets, plyfile, pandas, pyyaml, tqdm, tree, unzip, zip
, autoPatchelfHook, pytorchWithCuda, libtensorflow-bin, libusb, cudaPackages
, libGL }:
let
addict = buildPythonPackage {
pname = "addict";
version = "2.4.0";
@rowanG077
rowanG077 / BlockRamHack.hs
Last active June 24, 2019 12:10
clash compiler freeze
{-# LANGUAGE MagicHash #-}
module BlockRamHack where
import Data.Maybe (fromJust, isJust)
import Clash.Prelude
import qualified Clash.Explicit.Prelude as E
import Clash.Explicit.BlockRam (blockRam#)
@rowanG077
rowanG077 / manual-build
Created June 19, 2019 16:02
pythonocc nix
[nix-shell:~/cadquery]$ git clone https://github.com/tpaviot/pythonocc-core.git
Cloning into 'pythonocc-core'...
remote: Enumerating objects: 14342, done.
remote: Total 14342 (delta 0), reused 0 (delta 0), pack-reused 14342
Receiving objects: 100% (14342/14342), 59.13 MiB | 9.49 MiB/s, done.
Resolving deltas: 100% (11509/11509), done.
[nix-shell:~/cadquery]$ cd pythonocc-core
[nix-shell:~/cadquery/pythonocc-core]$ git checkout -t 0.18.1
Switched to a new branch '0.18.1'
@rowanG077
rowanG077 / de0-nano-soc-uart-working.dts
Last active June 1, 2019 14:53
de0-nano-soc-uart-working.dts
/dts-v1/;
/memreserve/ 0x0000000000000000 0x0000000000001000;
/ {
#address-cells = <0x1>;
#size-cells = <0x1>;
model = "Terasic DE-0(Atlas)";
compatible = "altr,socfpga-cyclone5", "altr,socfpga";
chosen {
@rowanG077
rowanG077 / de0-nano-soc-unmodified.dts
Created June 1, 2019 14:49
de0-nano-soc-unmodified.dts
/dts-v1/;
/memreserve/ 0x0000000000000000 0x0000000000001000;
/ {
#address-cells = <0x1>;
#size-cells = <0x1>;
model = "Terasic DE-0(Atlas)";
compatible = "altr,socfpga-cyclone5", "altr,socfpga";
chosen {