reduced_iter_mult.futil

import "primitives/core.futil";

component main() -> () {

  cells {
    q = std_reg(4); //multiplier (11)

    //will use these shifters and adders
    add_3bits = std_add(3);

    //will also use this slicer to check the last bit
    slicer = std_slice(4, 1);

    //for the while loop
    lt = std_lt(3); //counting to 4, b/c multiplying 4 bit numbers (4 = [100])
    i = std_reg(3); //counting to 4  (4 = [100])
  }

  wires {

    group cond_while {
      //lt compares i and 4
      lt.left = i.out;
      lt.right = 3'd4;
      cond_while[done] = 1'b1;
    }

    group incr_while {
      //i = i + 1
      i.write_en = 1'b1;
      add_3bits.left = i.out;
      add_3bits.right = 3'd1;
      i.in = add_3bits.out;
      incr_while[done] = i.done;
    }

    group cond_if {
      //get LSB of Q
      slicer.in = q.out;
      cond_if[done] = 1'b1;
    }

  }

  control {
    while lt.out with cond_while { //just 4 iterations (i starts as 0)
      seq {
        if slicer.out with cond_if { //there is a 1 in LSB of Q
          seq {}
        } else { //there is a 0 in LSB of Q
          seq {}
        }
        incr_while;
      }
    }
  }
}