A minimal table to compare the Espressif's MCU families.
ESP8266 | ESP32 | ESP32-S2 | ESP32-S3 | ESP32-C3 | ESP32-C6 | |
---|---|---|---|---|---|---|
Announcement Date | 2014, August | 2016, September | 2019, September | 2020, December | 2020, November | 2021, April |
Main processor | Tensilica L106 32-bit (up to 160MHz) | Tensilica Xtensa 32-bit LX6 (up to 240MHz) (optionally dual core) | Tensilica Xtensa 32-bit LX7 (up to 240MHz) | Tensilica Xtensa 32-bit LX7 dual core (up to 240MHz) | RISC-V 32-bit (up to 160MHz) | RISC-V 32-bit (up to 160MHz) |
SRAM | 160KB | 520KB | 320KB | 512KB | 400KB | 400KB |
ROM | 0 | 448KB | 128KB | 384KB | 384KB | 384KB |
JTAG | X | ✓ | ✓ | ? | ✓ | ✓ |
Cache | 32 KB instruction | 64KB | 8/16KB (configurable) | ? | 16KB | ? |
WiFi | Wi-Fi 4 (only up to 72.2Mbps) | Wi-Fi 4 | Wi-Fi 4 | Wi-Fi 4 | Wi-Fi 4 | Wi-Fi 6 |
Bluetooth | X | BLE 4.2 (upgrade to 5.0, with limitations) | X | BLE 5.0 | BLE 5.0 | BLE 5.0 |
Ethernet | X | ✓ | X | ? | X | ? |
RTC memory | 768B | 16KB | 16KB | 16KB | 8KB | ? |
PMU | ✓ | ✓ | ✓ | ? | ✓ | ? |
ULP coprocessor | X | ✓ | ULP-RISC-V | ? | X | ? |
Cryptographic Accelerator | X | SHA, RSA, AES, RNG | SHA, RSA, AES, RNG, HMAC, Digital Signature | SHA, RSA, AES, RNG, HMAC, Digital Signature | SHA, RSA, AES, RNG, HMAC, Digital Signature | SHA, RSA, AES, RNG, HMAC, Digital Signature |
Secure boot | X | ✓ | ✓ | ✓ | ✓ | ✓ |
Flash encryption | X | ✓ | XTS-AES-128/256 | ✓ | XTS-AES-128 | XTS-AES-128 |
SPI | 2 | 4 | 4 | ? | 3 | ? |
I2C | 1 | 2 | 2 | ? | 1 | ? |
I2S | 1 | 2 | 1 | ? | 1 | ? |
UART | 2 (one TX only) | 3 | 2 | ? | 2 | ? |
SDIO Host | 0 | 1 | 0 | 2 | 0 | 0 |
SDIO Slave | 0 | 1 | 0 | 0 | 0 | 0 |
GPIO | 17 | 34 | 43 | 44 | 22 | 22 |
LED PWM | 5 | 16 | 8 | ? | 6 | ? |
MCPWM | 0 | 6 | 0 | 2 | 0 | 0 |
Pulse counter | 0 | 8 | 4 | ? | 0 | X |
GDMA* | 0 | 0 | 0 | ? | 6 | ? |
USB | X | X | USB OTG 1.1 | ? | Serial/JTAG | ? |
TWAI** | 0 | 1 | 1 | ? | 1 | ? |
ADC | 1x 10-bit SAR | 2x 12-bit SAR, up to 18 channels | 2x 13-bit SAR, up to 20 channels | ? | 2x 12-bit SAR, up to 6 channels | ? |
DAC | X | 2x 8-bit | 2x 8-bit | ? | X | X |
RMT | 1x transmission + 1x reception | 8x transmission/reception | 4x transmission/reception | ? | 2x transmission + 2x reception | ? |
Timer | 2x 23-bit*** | 4x 64-bit | 4x 64-bit | ? | 2x 54-bit + 1x 52-bit | ? |
Temperature Sensor | ✓ | ✓ | ✓ | ? | ✓ | ? |
Hall Sensor | X | ✓ | X | ? | X | ? |
Touch Sensor | 0 | 10 | 14 | ? | X | ? |
* All the MCUs have some sort of DMA. However, if this field is not checked, it means that the user hasn't the direct control over DMA. With General DMA term, Espressif intends a specific DMA peripheral in full control of user. He will be responsible to manage such peripheral.
** In some old datasheet and documentation, it was referred as CAN bus.
*** A timer is dedicated to Wi-Fi, so you cannot freely use it.
For more details about specific models and variants, look at Espressif Product Selector.
The table will be updated as new information will be released. Contributions and suggestions are welcomed!
probably credit @fabianoriccardi (author of the content you forked) and describe your changes?
= I have no modifications. I only forked for ease of later reference (many times the original goes missing). Thanks for your suggestion, I'll definitely add credit to the original author.
clarify that this is comparing chips (SoCs) rather than modules (silver boxes). for example most modules will have fewer GPIOs than the chip itself offers?
= Correct, I'll add this clarification to the description.
replace all "0" and "X" with "-" which is a clearer indication of absence?
= I prefer to keep it as it is in the original.
I think we can fill in all the "?" now?
= Yes, but for the same reason as above, I haven't changed anything and recommend referring to a newer, more up-to-date source: https://gist.github.com/sekcompsci/2bf39e715d5fe47579fa184fa819f421?permalink_comment_id=4348602#gistcomment-4348602
I'd be happy to send you a diff or make a fork or something-- unfortunately gists don't support pull requests I think?
= Yes, unfortunately.