simple priority encoder on SystemVerilog to check if it is synthesizable in different software

prior_encod.sv

`timescale 1ns / 1ps

module prior_encod(
    input logic [11:0] sw,
    output logic [3:0] leds
    );
    always_comb begin
        if (sw == 12'b0) begin
            leds = 4'b0;
        end else begin
            for(int i=0;i<12;i++) begin
                if (sw[i] == 1'b1) begin
                    leds = i;
                end
            end
        end
    end
endmodule