smirnovich

`timescale 1ns / 1ps

module prior_encod(
    input logic [11:0] sw,
    output logic [3:0] leds
    );
    always_comb begin
        if (sw == 12'b0) begin
            leds = 4'b0;
        end else begin

smirnovich

library ieee;
use ieee.std_logic_1164.all;

entity simple_process is
port(
  cmd : in std_logic;
  d1 : in std_logic_vector(3 downto 0);
  d2 : in std_logic_vector(3 downto 0);
  o1 : out std_logic_vector(3 downto 0)
);

smirnovich

<...>
type t_my_type is (idle, green, yellow, blue);
signal fsm_lights : t_my_type :=idle;
<...>

smirnovich

library IEEE;
use IEEE.std_logic_1164.all;

use std.env.stop;

entity testbench is
end entity;


architecture tb of testbench is

smirnovich

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity demo1 is
	port(
    	data0 : in std_logic;
        data1 : in std_logic_vector(7 downto 0);
        data2 : in std_logic_vector(7 downto 0);
        my_out : out std_logic_vector(8 downto 0)

smirnovich

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity flag_example is
 port(
   data        : in std_logic_vector(3 downto 0);
   flag        : in std_logic;
   o2          : out std_logic_vector(3 downto 0)
  );
end entity;

smirnovich

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sig_seq is
 port(
   clk : in std_logic;
   a1  : in std_logic;
   a2  : in std_logic;
   o1  : out std_logic
  );

smirnovich

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sig_example is
 port(
   a1 : in std_logic;
   a2 : in std_logic;
   o1 : out std_logic;
   o2 : out std_logic
  );

smirnovich

library ieee;
use ieee.std_logic_1164.all;

entity upgraded_trigger is
  port(
    clk : in std_logic;
    rst : in std_logic
    d : in std_logic;
    en : in std_logic;
    q : out std_logic

smirnovich

library ieee;
use ieee.std_logic_1164.all;
entity simple_trigger is
  port(
    clk : in std_logic;
    d   : in std_logic;
    q   : out std_logic
  );
end entity;