Simple VHDL trigger

simple_trigger.vhd

library ieee;
use ieee.std_logic_1164.all;
entity simple_trigger is
  port(
    clk : in std_logic;
    d   : in std_logic;
    q   : out std_logic
  );
end entity;

architecture rtl of simple_trigger is
begin
  process(clk)
  begin
    if(rising_edge(clk)) then
      q <= d;
    end if;
  end process;
end rtl;