demo file to test

demo1.vhd

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity demo1 is
	port(
    	data0 : in std_logic;
        data1 : in std_logic_vector(7 downto 0);
        data2 : in std_logic_vector(7 downto 0);
        my_out : out std_logic_vector(8 downto 0)
        );
end entity;

architecture rtl of demo1 is
	signal sum : std_logic_vector(8 downto 0);
        signal sub : std_logic_vector(8 downto 0);
    
begin    
process(all)
begin
    sum <= std_logic_vector(signed(data1(7) & data1) + signed(data2(7) & data2));
    sub <= std_logic_vector(signed(data1(7) & data1) - signed(data2(7) & data2));
    if data0 = '1' then
    	my_out <= sum;
    else
    	my_out <= sub;
    end if;
end process;
end rtl;