Testbench for demo1

testbench.vhd

library IEEE;
use IEEE.std_logic_1164.all;

use std.env.stop;

entity testbench is
end entity;


architecture tb of testbench is
	signal data0 : std_logic;
	signal dataa : std_logic_vector(7 downto 0);
	signal data2 : std_logic_vector(7 downto 0);
	signal my_out : std_logic_vector(8 downto 0);
begin
	dut : entity work.design(rtl)
    port map(
    	data0=>data0,
        data1=>data1,
        data2=>data2,
        my_out=>my_out
    );
process
begin
    data0 <= '0';
    data1 <= 8x"7";
    data2 <= 8x"7";
    wait for 1 ns;
    if my_out = 9x"0" then
          report "Test passed SUCCESS";
      else
          report "Test passed ERROR" severity warning;
      end if;
      stop;
end process;
end tb;