VHDL process block example

simple_process.vhd

library ieee;
use ieee.std_logic_1164.all;

entity simple_process is
port(
  cmd : in std_logic;
  d1 : in std_logic_vector(3 downto 0);
  d2 : in std_logic_vector(3 downto 0);
  o1 : out std_logic_vector(3 downto 0)
);
end entity;
architecture rtl of simple_process is
  signal dd : std_logic_vector(3 downto 0);
begin
  o1 <= not(dd);
  process(d1,d2,cmd)
  begin
    if (cmd = '1') then
      dd <= d1 and d2;
    else
      dd <= d1 or d2;
    end if;
  end process;
end rtl;