More advance VHDL trigger with async reset and sync enable

upgraded_trigger.vhd

library ieee;
use ieee.std_logic_1164.all;

entity upgraded_trigger is
  port(
    clk : in std_logic;
    rst : in std_logic
    d : in std_logic;
    en : in std_logic;
    q : out std_logic
  );
end entity;

architecture rtl of upgraded_trigger is
begin
  process(clk)
  begin
    if (rst = '1') then    --asynq reset
      q <= '0';
    elsif(rising_edge(clk)) then
      if (en = '1') then
        q<=d;
      end if;
    end if;
  end process;
end rtl;