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# Copyright (c) 2024 Victor Suarez Rovere <suarezvictor@gmail.com>
# SPDX-License-Identifier: AGPL-3.0-only
# code portions from LiteX framework (C) Enjoy-Digital https://github.com/enjoy-digital/litex

import sys
import argparse

from migen import *
from litex.soc.cores.clock import *
from litex.soc.integration.builder import *

suarezvictor

# This is an nmigen delay line for ECP5 FPGAs using the open source toolchain. It strings together a series of
# manually placed carry chains into a "thermometer." It returns a signal that's (length) long that represents
# the chain "snapshotted" at the primary clock domain (using the flip flops colocated in the slice).
#
# This can be used in a Time to Digital Converter (i.e. to measure the time between to events) or in
# an ADC by comparing (with LVDS) a signal to a reference signal.
#
# Note that the bit precision (read: delay per carry element) varies as a function of temperature. On 
# a LFE5U-25F-8MG285C, I've measure delay times of approximately 43ps on average. Due to assorted reasons,
# the delay time will vary between bits and due to variations in routing (even when manually places), you might 

suarezvictor

# This is an nmigen delay line for ECP5 FPGAs using the open source toolchain. It strings together a series of
# manually placed carry chains into a "thermometer." It returns a signal that's (length) long that represents
# the chain "snapshotted" at the primary clock domain (using the flip flops colocated in the slice).
#
# This can be used in a Time to Digital Converter (i.e. to measure the time between to events) or in
# an ADC by comparing (with LVDS) a signal to a reference signal.
#
# Note that the bit precision (read: delay per carry element) varies as a function of temperature. On 
# a LFE5U-25F-8MG285C, I've measure delay times of approximately 43ps on average. Due to assorted reasons,
# the delay time will vary between bits and due to variations in routing (even when manually places), you might 

suarezvictor

//Copyright (C) 2023 Victor Suarez Rovere <suarezvictor@gmail.com>

#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>

typedef uint32_t uint18_t, uint19_t, uint27_t, uint23_t;
typedef uint16_t uint9_t, uint10_t, uint15_t;
typedef uint8_t uint1_t;

suarezvictor

//comparison operator using adders
//(C) 2023 Victor Suarez Rovere

#include <stdio.h>


//select type (all were tested)
typedef unsigned char type;
//typedef signed char type;
//typedef unsigned short type;

suarezvictor

//original at https://gist.github.com/a1k0n/8ea6516b4946ab36348fb61703dc3194

#include <stdint.h>
#include <stdio.h>
#include <string.h>
#include <unistd.h>
#include <math.h>

#define debug(...)
//#define debug printf

suarezvictor

// Automatically generated C++ file on Sat Aug 26 14:20:23 2023
//
// To build with Digital Mars C++ Compiler:
//
//    dmc -mn -WD test0_x1.cpp kernel32.lib

#include <stdio.h>
#include <malloc.h>
#include <stdarg.h>
#include <time.h>

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/* originally from https://github.com/bl0x/learn-fpga-amaranth/blob/main/18_mandelbrot/cpu.py */
from amaranth import *

class CPU(Elaboratable):

    def __init__(self):
        self.mem_addr = Signal(32)
        self.mem_rstrb = Signal()
        self.mem_rdata = Signal(32)
        self.mem_wdata = Signal(32)

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#original source https://github.com/bl0x/learn-fpga-amaranth/blob/main/01_blink/soc.py

from amaranth import *

# Any Elaboratable class is used to generate HDL output
class SOC(Elaboratable):

    def __init__(self):

        # A Signal is usually created with its number of bits (default = 1).

suarezvictor

//This code was generated by Verilator and manually adapted to C++
//Adaptations by Victor Suarez Rovere <suarezvictor@gmail.com>
//original sources https://github.com/BrunoLevy/learn-fpga/blob/master/FemtoRV/README.md
//by Bruno Levy -  BSD-3-Clause license

#include "cpu.h"

void cpu_instance::simstep0(uint32_t mbus_rdata0)
{
    uint5 __Vdlyvdim0__registerFile__v0;