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suarezvictor/cpu.py

Created February 28, 2023 19:43
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RISC-V CPU manyally converted from Verilog to Amaranth, then automatically back to Verilog
Raw
cpu.py
/* originally from https://github.com/bl0x/learn-fpga-amaranth/blob/main/18_mandelbrot/cpu.py */
from amaranth import *
class CPU(Elaboratable):
def __init__(self):
self.mem_addr = Signal(32)
self.mem_rstrb = Signal()
self.mem_rdata = Signal(32)
self.mem_wdata = Signal(32)
self.mem_wmask = Signal(4)
self.x10 = Signal(32)
self.fsm = None
def elaborate(self, platform):
m = Module()
# Program counter
pc = Signal(32)
self.pc = pc
# Memory
mem_rdata = self.mem_rdata
# Current instruction
instr = Signal(32, reset=0b0110011)
self.instr = instr
# Register bank
regs = Array([Signal(32, name="x"+str(x)) for x in range(32)])
self.regs = regs
rs1 = Signal(32)
rs2 = Signal(32)
# ALU registers
aluOut = Signal(32)
takeBranch = Signal(32)
# Opcode decoder
# It is nice to have these as actual signals for simulation
isALUreg = Signal()
isALUimm = Signal()
isBranch = Signal()
isJALR = Signal()
isJAL = Signal()
isAUIPC = Signal()
isLUI = Signal()
isLoad = Signal()
isStore = Signal()
isSystem = Signal()
m.d.comb += [
isALUreg.eq(instr[0:7] == 0b0110011),
isALUimm.eq(instr[0:7] == 0b0010011),
isBranch.eq(instr[0:7] == 0b1100011),
isJALR.eq(instr[0:7] == 0b1100111),
isJAL.eq(instr[0:7] == 0b1101111),
isAUIPC.eq(instr[0:7] == 0b0010111),
isLUI.eq(instr[0:7] == 0b0110111),
isLoad.eq(instr[0:7] == 0b0000011),
isStore.eq(instr[0:7] == 0b0100011),
isSystem.eq(instr[0:7] == 0b1110011)
]
self.isALUreg = isALUreg
self.isALUimm = isALUimm
self.isBranch = isBranch
self.isLoad = isLoad
self.isStore = isStore
self.isSystem = isSystem
# Extend a signal with a sign bit repeated n times
def SignExtend(signal, sign, n):
return Cat(signal, Repl(sign, n))
# Immediate format decoder
Uimm = Signal(32)
Iimm = Signal(32)
Simm = Signal(32)
Bimm = Signal(32)
Jimm = Signal(32)
m.d.comb += [
Uimm.eq(Cat(Repl(0, 12), instr[12:32])),
Iimm.eq(Cat(instr[20:31], Repl(instr[31], 21))),
Simm.eq(Cat(instr[7:12], instr[25:31], Repl(instr[31], 21))),
Bimm.eq(Cat(0, instr[8:12], instr[25:31], instr[7],
Repl(instr[31], 20))),
Jimm.eq(Cat(0, instr[21:31], instr[20], instr[12:20],
Repl(instr[31], 12)))
]
self.Iimm = Iimm
# Register addresses decoder
rs1Id = instr[15:20]
rs2Id = instr[20:25]
rdId = instr[7:12]
self.rdId = rdId
self.rs1Id = rs1Id
self.rs2Id = rs2Id
# Function code decdore
funct3 = instr[12:15]
funct7 = instr[25:32]
self.funct3 = funct3
# ALU
aluIn1 = Signal.like(rs1)
aluIn2 = Signal.like(rs2)
shamt = Signal(5)
aluMinus = Signal(33)
aluPlus = Signal.like(aluIn1)
m.d.comb += [
aluIn1.eq(rs1),
aluIn2.eq(Mux((isALUreg | isBranch), rs2, Iimm)),
shamt.eq(Mux(isALUreg, rs2[0:5], instr[20:25]))
]
m.d.comb += [
aluMinus.eq(Cat(~aluIn2, C(1,1)) + Cat(aluIn1, C(0,1)) + 1),
aluPlus.eq(aluIn1 + aluIn2)
]
EQ = aluMinus[0:32] == 0
LTU = aluMinus[32]
LT = Mux((aluIn1[31] ^ aluIn2[31]), aluIn1[31], aluMinus[32])
def flip32(x):
a = [x[i] for i in range(0, 32)]
return Cat(*reversed(a))
# TODO: check these again!
shifter_in = Mux(funct3 == 0b001, flip32(aluIn1), aluIn1)
shifter = (Cat(shifter_in,
(instr[30] & aluIn1[31]))).as_signed() >> aluIn2[0:5]
leftshift = flip32(shifter)
with m.Switch(funct3) as alu:
with m.Case(0b000):
m.d.comb += aluOut.eq(Mux(funct7[5] & instr[5],
aluMinus[0:32], aluPlus))
with m.Case(0b001):
m.d.comb += aluOut.eq(leftshift)
with m.Case(0b010):
m.d.comb += aluOut.eq(LT)
with m.Case(0b011):
m.d.comb += aluOut.eq(LTU)
with m.Case(0b100):
m.d.comb += aluOut.eq(aluIn1 ^ aluIn2)
with m.Case(0b101):
m.d.comb += aluOut.eq(shifter)
with m.Case(0b110):
m.d.comb += aluOut.eq(aluIn1 | aluIn2)
with m.Case(0b111):
m.d.comb += aluOut.eq(aluIn1 & aluIn2)
with m.Switch(funct3) as alu_branch:
with m.Case(0b000):
m.d.comb += takeBranch.eq(EQ)
with m.Case(0b001):
m.d.comb += takeBranch.eq(~EQ)
with m.Case(0b100):
m.d.comb += takeBranch.eq(LT)
with m.Case(0b101):
m.d.comb += takeBranch.eq(~LT)
with m.Case(0b110):
m.d.comb += takeBranch.eq(LTU)
with m.Case(0b111):
m.d.comb += takeBranch.eq(~LTU)
with m.Case("---"):
m.d.comb += takeBranch.eq(0)
# Next program counter is either next intstruction or depends on
# jump target
pcPlusImm = pc + Mux(instr[3], Jimm[0:32],
Mux(instr[4], Uimm[0:32],
Bimm[0:32]))
pcPlus4 = pc + 4
nextPc = Mux(((isBranch & takeBranch) | isJAL), pcPlusImm,
Mux(isJALR, Cat(C(0, 1), aluPlus[1:32]),
pcPlus4))
# Main state machine
with m.FSM(reset="FETCH_INSTR") as fsm:
self.fsm = fsm
with m.State("FETCH_INSTR"):
m.next = "WAIT_INSTR"
with m.State("WAIT_INSTR"):
m.d.sync += instr.eq(self.mem_rdata)
m.next = ("FETCH_REGS")
with m.State("FETCH_REGS"):
m.d.sync += [
rs1.eq(regs[rs1Id]),
rs2.eq(regs[rs2Id])
]
m.next = "EXECUTE"
with m.State("EXECUTE"):
with m.If(~isSystem):
m.d.sync += pc.eq(nextPc)
with m.If(isLoad):
m.next = "LOAD"
with m.Elif(isStore):
m.next = "STORE"
with m.Else():
m.next = "FETCH_INSTR"
with m.State("LOAD"):
m.next = "WAIT_DATA"
with m.State("WAIT_DATA"):
m.next = "FETCH_INSTR"
with m.State("STORE"):
m.next = "FETCH_INSTR"
## Load and store
loadStoreAddr = Signal(32)
m.d.comb += loadStoreAddr.eq(rs1 + Mux(isStore, Simm, Iimm))
# Load
memByteAccess = Signal()
memHalfwordAccess = Signal()
loadHalfword = Signal(16)
loadByte = Signal(8)
loadSign = Signal()
loadData = Signal(32)
m.d.comb += [
memByteAccess.eq(funct3[0:2] == C(0,2)),
memHalfwordAccess.eq(funct3[0:2] == C(1,2)),
loadHalfword.eq(Mux(loadStoreAddr[1], mem_rdata[16:32],
mem_rdata[0:16])),
loadByte.eq(Mux(loadStoreAddr[0], loadHalfword[8:16],
loadHalfword[0:8])),
loadSign.eq(~funct3[2] & Mux(memByteAccess, loadByte[7],
loadHalfword[15])),
loadData.eq(
Mux(memByteAccess, SignExtend(loadByte, loadSign, 24),
Mux(memHalfwordAccess, SignExtend(loadHalfword,
loadSign, 16),
mem_rdata)))
]
# Store
m.d.comb += [
self.mem_wdata[ 0: 8].eq(rs2[0:8]),
self.mem_wdata[ 8:16].eq(
Mux(loadStoreAddr[0], rs2[0:8], rs2[8:16])),
self.mem_wdata[16:24].eq(
Mux(loadStoreAddr[1], rs2[0:8], rs2[16:24])),
self.mem_wdata[24:32].eq(
Mux(loadStoreAddr[0], rs2[0:8],
Mux(loadStoreAddr[1], rs2[8:16], rs2[24:32])))
]
store_wmask = Signal(4)
m.d.comb += store_wmask.eq(
Mux(memByteAccess,
Mux(loadStoreAddr[1],
Mux(loadStoreAddr[0], 0b1000, 0b0100),
Mux(loadStoreAddr[0], 0b0010, 0b0001)
),
Mux(memHalfwordAccess,
Mux(loadStoreAddr[1], 0b1100, 0b0011),
0b1111)
)
)
# Wire memory address to pc or loadStoreAddr
m.d.comb += [
self.mem_addr.eq(
Mux(fsm.ongoing("WAIT_INSTR") | fsm.ongoing("FETCH_INSTR"),
pc, loadStoreAddr)),
self.mem_rstrb.eq(fsm.ongoing("FETCH_INSTR") | fsm.ongoing("LOAD")),
self.mem_wmask.eq(Repl(fsm.ongoing("STORE"), 4) & store_wmask)
]
# Register write back
writeBackData = Mux((isJAL | isJALR), pcPlus4,
Mux(isLUI, Uimm,
Mux(isAUIPC, pcPlusImm,
Mux(isLoad, loadData,
aluOut))))
writeBackEn = ((fsm.ongoing("EXECUTE") & ~isBranch & ~isStore & ~isLoad)
| fsm.ongoing("WAIT_DATA"))
self.writeBackData = writeBackData
with m.If(writeBackEn & (rdId != 0)):
m.d.sync += regs[rdId].eq(writeBackData)
# Also assign to debug output to see what is happening
with m.If(rdId == 10):
m.d.sync += self.x10.eq(writeBackData)
return m
Raw
cpu.v
/* originally from https://github.com/bl0x/learn-fpga-amaranth/blob/main/18_mandelbrot/cpu.py */
/* Generated by Yosys 0.24+10 (git sha1 3ebc50dee, clang 11.0.1-2 -fPIC -Os) */
(* \amaranth.hierarchy = "top.soc.cpu" *)
(* generator = "Amaranth" *)
module cpu(mem_wmask, mem_rstrb, mem_wdata, mem_rdata, slow_clk, slow_rst, mem_addr);
reg \$auto$verilog_backend.cc:2083:dump_module$1 = 0;
wire \$1 ;
wire \$100 ;
wire [32:0] \$1002 ;
wire [32:0] \$1003 ;
wire [32:0] \$1005 ;
wire [31:0] \$1007 ;
wire [31:0] \$1009 ;
wire [32:0] \$1011 ;
wire [32:0] \$1013 ;
wire [31:0] \$1014 ;
wire [32:0] \$1017 ;
wire [32:0] \$1019 ;
wire [32:0] \$102 ;
wire [32:0] \$1021 ;
wire \$1022 ;
wire [32:0] \$1025 ;
wire [32:0] \$1026 ;
wire [32:0] \$1028 ;
wire [31:0] \$1030 ;
wire [31:0] \$1032 ;
wire [32:0] \$1034 ;
wire [32:0] \$1036 ;
wire [31:0] \$1037 ;
wire [32:0] \$104 ;
wire [32:0] \$1040 ;
wire [32:0] \$1042 ;
wire [32:0] \$1044 ;
wire \$1045 ;
wire [32:0] \$1048 ;
wire [32:0] \$1049 ;
wire [31:0] \$105 ;
wire [32:0] \$1051 ;
wire [31:0] \$1053 ;
wire [31:0] \$1055 ;
wire [32:0] \$1057 ;
wire [32:0] \$1059 ;
wire \$106 ;
wire [31:0] \$1060 ;
wire [32:0] \$1063 ;
wire [32:0] \$1065 ;
wire [32:0] \$1067 ;
wire \$1068 ;
wire [32:0] \$1071 ;
wire [32:0] \$1072 ;
wire [32:0] \$1074 ;
wire [31:0] \$1076 ;
wire [31:0] \$1078 ;
wire [32:0] \$1080 ;
wire [32:0] \$1082 ;
wire [31:0] \$1083 ;
wire [32:0] \$1086 ;
wire [32:0] \$1088 ;
wire \$109 ;
wire [32:0] \$1090 ;
wire \$1091 ;
wire [32:0] \$1094 ;
wire [32:0] \$1095 ;
wire [32:0] \$1097 ;
wire [31:0] \$1099 ;
wire \$11 ;
wire [31:0] \$1101 ;
wire [32:0] \$1103 ;
wire [32:0] \$1105 ;
wire [31:0] \$1106 ;
wire [32:0] \$1109 ;
wire [32:0] \$111 ;
wire [32:0] \$1111 ;
wire [32:0] \$1113 ;
wire \$1114 ;
wire [32:0] \$1117 ;
wire [32:0] \$1118 ;
wire [32:0] \$1120 ;
wire [31:0] \$1122 ;
wire [31:0] \$1124 ;
wire [32:0] \$1126 ;
wire [32:0] \$1128 ;
wire [31:0] \$1129 ;
wire [32:0] \$113 ;
wire [32:0] \$1132 ;
wire [32:0] \$1134 ;
wire [32:0] \$1136 ;
wire \$1137 ;
wire [31:0] \$114 ;
wire [32:0] \$1140 ;
wire [32:0] \$1141 ;
wire [32:0] \$1143 ;
wire [31:0] \$1145 ;
wire [31:0] \$1147 ;
wire [32:0] \$1149 ;
wire \$115 ;
wire [32:0] \$1151 ;
wire [31:0] \$1152 ;
wire [32:0] \$1155 ;
wire [32:0] \$1157 ;
wire [32:0] \$1159 ;
wire \$1160 ;
wire [32:0] \$1163 ;
wire [32:0] \$1164 ;
wire [32:0] \$1166 ;
wire [31:0] \$1168 ;
wire [31:0] \$1170 ;
wire [32:0] \$1172 ;
wire [32:0] \$1174 ;
wire [31:0] \$1175 ;
wire [32:0] \$1178 ;
wire \$118 ;
wire [32:0] \$1180 ;
wire [32:0] \$1182 ;
wire \$1183 ;
wire [32:0] \$1186 ;
wire [32:0] \$1187 ;
wire [32:0] \$1189 ;
wire [31:0] \$1191 ;
wire [31:0] \$1193 ;
wire [32:0] \$1195 ;
wire [32:0] \$1197 ;
wire [31:0] \$1198 ;
wire [32:0] \$120 ;
wire [32:0] \$1201 ;
wire [32:0] \$1203 ;
wire [32:0] \$1205 ;
wire \$1206 ;
wire [32:0] \$1209 ;
wire [32:0] \$1210 ;
wire [32:0] \$1212 ;
wire [31:0] \$1214 ;
wire [31:0] \$1216 ;
wire [32:0] \$1218 ;
wire [32:0] \$122 ;
wire [32:0] \$1220 ;
wire [31:0] \$1221 ;
wire [32:0] \$1224 ;
wire [32:0] \$1226 ;
wire [32:0] \$1228 ;
wire \$1229 ;
wire [31:0] \$123 ;
wire [32:0] \$1232 ;
wire [32:0] \$1233 ;
wire [32:0] \$1235 ;
wire [31:0] \$1237 ;
wire [31:0] \$1239 ;
wire \$124 ;
wire [32:0] \$1241 ;
wire [32:0] \$1243 ;
wire [31:0] \$1244 ;
wire [32:0] \$1247 ;
wire [32:0] \$1249 ;
wire [32:0] \$1251 ;
wire \$1252 ;
wire \$1256 ;
wire \$1258 ;
wire \$1260 ;
wire \$1262 ;
wire \$1264 ;
wire \$1266 ;
wire \$1268 ;
wire \$127 ;
wire \$1270 ;
wire \$1272 ;
wire \$1274 ;
wire \$1276 ;
wire \$1278 ;
wire [32:0] \$1280 ;
wire [32:0] \$1281 ;
wire [32:0] \$1283 ;
wire [31:0] \$1285 ;
wire [31:0] \$1287 ;
wire [32:0] \$1289 ;
wire [32:0] \$129 ;
wire [32:0] \$1291 ;
wire [31:0] \$1292 ;
wire [32:0] \$1295 ;
wire [32:0] \$1297 ;
wire [32:0] \$1299 ;
wire \$13 ;
wire \$1300 ;
wire [32:0] \$131 ;
wire [31:0] \$132 ;
wire \$133 ;
wire \$136 ;
wire [32:0] \$138 ;
wire [32:0] \$140 ;
wire [31:0] \$141 ;
wire \$142 ;
wire \$145 ;
wire [32:0] \$147 ;
wire [32:0] \$149 ;
wire \$15 ;
wire [31:0] \$150 ;
wire \$151 ;
wire \$154 ;
wire [32:0] \$156 ;
wire [32:0] \$158 ;
wire [31:0] \$159 ;
wire \$160 ;
wire \$163 ;
wire [32:0] \$165 ;
wire [32:0] \$167 ;
wire [31:0] \$168 ;
wire \$169 ;
wire \$17 ;
wire \$172 ;
wire [32:0] \$174 ;
wire [32:0] \$176 ;
wire [31:0] \$177 ;
wire \$178 ;
wire \$181 ;
wire [32:0] \$183 ;
wire [32:0] \$185 ;
wire [31:0] \$186 ;
wire \$187 ;
wire \$19 ;
wire \$190 ;
wire [32:0] \$192 ;
wire [32:0] \$194 ;
wire [31:0] \$195 ;
wire \$196 ;
wire \$199 ;
wire [32:0] \$201 ;
wire [32:0] \$203 ;
wire [31:0] \$204 ;
wire \$205 ;
wire \$208 ;
wire [31:0] \$21 ;
wire [32:0] \$210 ;
wire [32:0] \$212 ;
wire [31:0] \$213 ;
wire \$214 ;
wire \$217 ;
wire [32:0] \$219 ;
wire \$22 ;
wire [32:0] \$221 ;
wire [31:0] \$222 ;
wire \$223 ;
wire \$226 ;
wire [32:0] \$228 ;
wire [32:0] \$230 ;
wire [31:0] \$231 ;
wire \$232 ;
wire \$235 ;
wire [32:0] \$237 ;
wire [32:0] \$239 ;
wire [31:0] \$240 ;
wire \$241 ;
wire \$244 ;
wire [32:0] \$246 ;
wire [32:0] \$248 ;
wire [31:0] \$249 ;
wire [4:0] \$25 ;
wire \$250 ;
wire \$253 ;
wire [32:0] \$255 ;
wire [32:0] \$257 ;
wire [31:0] \$258 ;
wire \$259 ;
wire \$262 ;
wire [32:0] \$264 ;
wire [32:0] \$266 ;
wire [31:0] \$267 ;
wire \$268 ;
wire [34:0] \$27 ;
wire \$271 ;
wire [32:0] \$273 ;
wire [32:0] \$275 ;
wire [31:0] \$276 ;
wire \$277 ;
wire [31:0] \$28 ;
wire \$280 ;
wire [32:0] \$282 ;
wire [32:0] \$284 ;
wire [31:0] \$285 ;
wire \$286 ;
wire \$289 ;
wire [32:0] \$291 ;
wire [32:0] \$293 ;
wire [31:0] \$294 ;
wire \$295 ;
wire \$298 ;
wire \$3 ;
wire [33:0] \$30 ;
wire [32:0] \$300 ;
wire [32:0] \$302 ;
wire [31:0] \$303 ;
wire \$304 ;
wire \$307 ;
wire [32:0] \$309 ;
wire [32:0] \$311 ;
wire [31:0] \$312 ;
wire \$313 ;
wire \$316 ;
wire [32:0] \$318 ;
wire [34:0] \$32 ;
wire [32:0] \$320 ;
wire [31:0] \$321 ;
wire \$322 ;
wire \$325 ;
wire [32:0] \$327 ;
wire [31:0] \$329 ;
wire \$330 ;
wire \$331 ;
wire [31:0] \$335 ;
wire [31:0] \$337 ;
wire [32:0] \$339 ;
wire [32:0] \$34 ;
wire [31:0] \$340 ;
wire \$341 ;
wire \$344 ;
wire [32:0] \$346 ;
wire [31:0] \$348 ;
wire [32:0] \$35 ;
wire [31:0] \$350 ;
wire [31:0] \$352 ;
wire \$353 ;
wire [31:0] \$356 ;
wire \$357 ;
wire \$358 ;
wire [31:0] \$362 ;
wire \$363 ;
wire \$364 ;
wire [31:0] \$368 ;
wire \$369 ;
wire [31:0] \$37 ;
wire \$370 ;
wire \$371 ;
wire [31:0] \$376 ;
wire [31:0] \$378 ;
wire \$379 ;
wire \$38 ;
wire \$382 ;
wire [32:0] \$384 ;
wire [31:0] \$385 ;
wire [31:0] \$387 ;
wire [32:0] \$389 ;
wire [32:0] \$391 ;
wire [32:0] \$393 ;
wire [32:0] \$395 ;
wire [32:0] \$397 ;
wire \$398 ;
wire [31:0] \$399 ;
wire [31:0] \$401 ;
wire [32:0] \$405 ;
wire [31:0] \$406 ;
wire [32:0] \$408 ;
wire [32:0] \$41 ;
wire \$410 ;
wire \$412 ;
wire [15:0] \$414 ;
wire [7:0] \$416 ;
wire \$418 ;
wire [31:0] \$42 ;
wire \$420 ;
wire \$422 ;
wire [31:0] \$424 ;
wire [31:0] \$426 ;
wire [7:0] \$428 ;
wire \$43 ;
wire [7:0] \$430 ;
wire [7:0] \$432 ;
wire [7:0] \$434 ;
wire [3:0] \$436 ;
wire [3:0] \$438 ;
wire [1:0] \$439 ;
wire [3:0] \$442 ;
wire [3:0] \$444 ;
wire [3:0] \$446 ;
wire [3:0] \$448 ;
wire [31:0] \$450 ;
wire \$451 ;
wire \$453 ;
wire \$455 ;
wire \$458 ;
wire \$46 ;
wire \$460 ;
wire \$462 ;
wire \$464 ;
wire \$466 ;
wire \$468 ;
wire \$470 ;
wire [3:0] \$472 ;
wire \$474 ;
wire \$476 ;
wire \$478 ;
wire [32:0] \$48 ;
wire \$480 ;
wire \$482 ;
wire \$484 ;
wire \$486 ;
wire \$488 ;
wire \$490 ;
wire \$492 ;
wire \$494 ;
wire [32:0] \$496 ;
wire [32:0] \$497 ;
wire [32:0] \$499 ;
wire \$5 ;
wire [32:0] \$50 ;
wire [31:0] \$501 ;
wire [31:0] \$503 ;
wire [32:0] \$505 ;
wire [32:0] \$507 ;
wire [31:0] \$508 ;
wire [31:0] \$51 ;
wire [32:0] \$511 ;
wire [32:0] \$513 ;
wire [32:0] \$515 ;
wire \$516 ;
wire [32:0] \$519 ;
wire \$52 ;
wire [32:0] \$520 ;
wire [32:0] \$522 ;
wire [31:0] \$524 ;
wire [31:0] \$526 ;
wire [32:0] \$528 ;
wire [32:0] \$530 ;
wire [31:0] \$531 ;
wire [32:0] \$534 ;
wire [32:0] \$536 ;
wire [32:0] \$538 ;
wire \$539 ;
wire [32:0] \$542 ;
wire [32:0] \$543 ;
wire [32:0] \$545 ;
wire [31:0] \$547 ;
wire [31:0] \$549 ;
wire \$55 ;
wire [32:0] \$551 ;
wire [32:0] \$553 ;
wire [31:0] \$554 ;
wire [32:0] \$557 ;
wire [32:0] \$559 ;
wire [32:0] \$561 ;
wire \$562 ;
wire [32:0] \$565 ;
wire [32:0] \$566 ;
wire [32:0] \$568 ;
wire [32:0] \$57 ;
wire [31:0] \$570 ;
wire [31:0] \$572 ;
wire [32:0] \$574 ;
wire [32:0] \$576 ;
wire [31:0] \$577 ;
wire [32:0] \$580 ;
wire [32:0] \$582 ;
wire [32:0] \$584 ;
wire \$585 ;
wire [32:0] \$588 ;
wire [32:0] \$589 ;
wire [32:0] \$59 ;
wire [32:0] \$591 ;
wire [31:0] \$593 ;
wire [31:0] \$595 ;
wire [32:0] \$597 ;
wire [32:0] \$599 ;
wire [31:0] \$60 ;
wire [31:0] \$600 ;
wire [32:0] \$603 ;
wire [32:0] \$605 ;
wire [32:0] \$607 ;
wire \$608 ;
wire \$61 ;
wire [32:0] \$611 ;
wire [32:0] \$612 ;
wire [32:0] \$614 ;
wire [31:0] \$616 ;
wire [31:0] \$618 ;
wire [32:0] \$620 ;
wire [32:0] \$622 ;
wire [31:0] \$623 ;
wire [32:0] \$626 ;
wire [32:0] \$628 ;
wire [32:0] \$630 ;
wire \$631 ;
wire [32:0] \$634 ;
wire [32:0] \$635 ;
wire [32:0] \$637 ;
wire [31:0] \$639 ;
wire \$64 ;
wire [31:0] \$641 ;
wire [32:0] \$643 ;
wire [32:0] \$645 ;
wire [31:0] \$646 ;
wire [32:0] \$649 ;
wire [32:0] \$651 ;
wire [32:0] \$653 ;
wire \$654 ;
wire [32:0] \$657 ;
wire [32:0] \$658 ;
wire [32:0] \$66 ;
wire [32:0] \$660 ;
wire [31:0] \$662 ;
wire [31:0] \$664 ;
wire [32:0] \$666 ;
wire [32:0] \$668 ;
wire [31:0] \$669 ;
wire [32:0] \$672 ;
wire [32:0] \$674 ;
wire [32:0] \$676 ;
wire \$677 ;
wire [32:0] \$68 ;
wire [32:0] \$680 ;
wire [32:0] \$681 ;
wire [32:0] \$683 ;
wire [31:0] \$685 ;
wire [31:0] \$687 ;
wire [32:0] \$689 ;
wire [31:0] \$69 ;
wire [32:0] \$691 ;
wire [31:0] \$692 ;
wire [32:0] \$695 ;
wire [32:0] \$697 ;
wire [32:0] \$699 ;
wire \$7 ;
wire \$70 ;
wire \$700 ;
wire [32:0] \$703 ;
wire [32:0] \$704 ;
wire [32:0] \$706 ;
wire [31:0] \$708 ;
wire [31:0] \$710 ;
wire [32:0] \$712 ;
wire [32:0] \$714 ;
wire [31:0] \$715 ;
wire [32:0] \$718 ;
wire [32:0] \$720 ;
wire [32:0] \$722 ;
wire \$723 ;
wire [32:0] \$726 ;
wire [32:0] \$727 ;
wire [32:0] \$729 ;
wire \$73 ;
wire [31:0] \$731 ;
wire [31:0] \$733 ;
wire [32:0] \$735 ;
wire [32:0] \$737 ;
wire [31:0] \$738 ;
wire [32:0] \$741 ;
wire [32:0] \$743 ;
wire [32:0] \$745 ;
wire \$746 ;
wire [32:0] \$749 ;
wire [32:0] \$75 ;
wire [32:0] \$750 ;
wire [32:0] \$752 ;
wire [31:0] \$754 ;
wire [31:0] \$756 ;
wire [32:0] \$758 ;
wire [32:0] \$760 ;
wire [31:0] \$761 ;
wire [32:0] \$764 ;
wire [32:0] \$766 ;
wire [32:0] \$768 ;
wire \$769 ;
wire [32:0] \$77 ;
wire [32:0] \$772 ;
wire [32:0] \$773 ;
wire [32:0] \$775 ;
wire [31:0] \$777 ;
wire [31:0] \$779 ;
wire [31:0] \$78 ;
wire [32:0] \$781 ;
wire [32:0] \$783 ;
wire [31:0] \$784 ;
wire [32:0] \$787 ;
wire [32:0] \$789 ;
wire \$79 ;
wire [32:0] \$791 ;
wire \$792 ;
wire [32:0] \$795 ;
wire [32:0] \$796 ;
wire [32:0] \$798 ;
wire [31:0] \$800 ;
wire [31:0] \$802 ;
wire [32:0] \$804 ;
wire [32:0] \$806 ;
wire [31:0] \$807 ;
wire [32:0] \$810 ;
wire [32:0] \$812 ;
wire [32:0] \$814 ;
wire \$815 ;
wire [32:0] \$818 ;
wire [32:0] \$819 ;
wire \$82 ;
wire [32:0] \$821 ;
wire [31:0] \$823 ;
wire [31:0] \$825 ;
wire [32:0] \$827 ;
wire [32:0] \$829 ;
wire [31:0] \$830 ;
wire [32:0] \$833 ;
wire [32:0] \$835 ;
wire [32:0] \$837 ;
wire \$838 ;
wire [32:0] \$84 ;
wire [32:0] \$841 ;
wire [32:0] \$842 ;
wire [32:0] \$844 ;
wire [31:0] \$846 ;
wire [31:0] \$848 ;
wire [32:0] \$850 ;
wire [32:0] \$852 ;
wire [31:0] \$853 ;
wire [32:0] \$856 ;
wire [32:0] \$858 ;
wire [32:0] \$86 ;
wire [32:0] \$860 ;
wire \$861 ;
wire [32:0] \$864 ;
wire [32:0] \$865 ;
wire [32:0] \$867 ;
wire [31:0] \$869 ;
wire [31:0] \$87 ;
wire [31:0] \$871 ;
wire [32:0] \$873 ;
wire [32:0] \$875 ;
wire [31:0] \$876 ;
wire [32:0] \$879 ;
wire \$88 ;
wire [32:0] \$881 ;
wire [32:0] \$883 ;
wire \$884 ;
wire [32:0] \$887 ;
wire [32:0] \$888 ;
wire [32:0] \$890 ;
wire [31:0] \$892 ;
wire [31:0] \$894 ;
wire [32:0] \$896 ;
wire [32:0] \$898 ;
wire [31:0] \$899 ;
wire \$9 ;
wire [32:0] \$902 ;
wire [32:0] \$904 ;
wire [32:0] \$906 ;
wire \$907 ;
wire \$91 ;
wire [32:0] \$910 ;
wire [32:0] \$911 ;
wire [32:0] \$913 ;
wire [31:0] \$915 ;
wire [31:0] \$917 ;
wire [32:0] \$919 ;
wire [32:0] \$921 ;
wire [31:0] \$922 ;
wire [32:0] \$925 ;
wire [32:0] \$927 ;
wire [32:0] \$929 ;
wire [32:0] \$93 ;
wire \$930 ;
wire [32:0] \$933 ;
wire [32:0] \$934 ;
wire [32:0] \$936 ;
wire [31:0] \$938 ;
wire [31:0] \$940 ;
wire [32:0] \$942 ;
wire [32:0] \$944 ;
wire [31:0] \$945 ;
wire [32:0] \$948 ;
wire [32:0] \$95 ;
wire [32:0] \$950 ;
wire [32:0] \$952 ;
wire \$953 ;
wire [32:0] \$956 ;
wire [32:0] \$957 ;
wire [32:0] \$959 ;
wire [31:0] \$96 ;
wire [31:0] \$961 ;
wire [31:0] \$963 ;
wire [32:0] \$965 ;
wire [32:0] \$967 ;
wire [31:0] \$968 ;
wire \$97 ;
wire [32:0] \$971 ;
wire [32:0] \$973 ;
wire [32:0] \$975 ;
wire \$976 ;
wire [32:0] \$979 ;
wire [32:0] \$980 ;
wire [32:0] \$982 ;
wire [31:0] \$984 ;
wire [31:0] \$986 ;
wire [32:0] \$988 ;
wire [32:0] \$990 ;
wire [31:0] \$991 ;
wire [32:0] \$994 ;
wire [32:0] \$996 ;
wire [32:0] \$998 ;
wire \$999 ;
wire [31:0] Bimm;
wire [31:0] Iimm;
wire [31:0] Jimm;
wire [31:0] Simm;
wire [31:0] Uimm;
wire [31:0] aluIn1;
wire [31:0] aluIn2;
wire [32:0] aluMinus;
reg [31:0] aluOut;
wire [31:0] aluPlus;
reg [2:0] fsm_state = 3'h0;
reg [2:0] \fsm_state$next ;
reg [31:0] instr = 32'd51;
reg [31:0] \instr$next ;
wire isALUimm;
wire isALUreg;
wire isAUIPC;
wire isBranch;
wire isJAL;
wire isJALR;
wire isLUI;
wire isLoad;
wire isStore;
wire isSystem;
wire [7:0] loadByte;
wire [31:0] loadData;
wire [15:0] loadHalfword;
wire loadSign;
wire [31:0] loadStoreAddr;
wire memByteAccess;
wire memHalfwordAccess;
output [31:0] mem_addr;
wire [31:0] mem_addr;
input [31:0] mem_rdata;
wire [31:0] mem_rdata;
output mem_rstrb;
wire mem_rstrb;
output [31:0] mem_wdata;
wire [31:0] mem_wdata;
output [3:0] mem_wmask;
wire [3:0] mem_wmask;
reg [31:0] pc = 32'd0;
reg [31:0] \pc$next ;
reg [31:0] rs1 = 32'd0;
reg [31:0] \rs1$next ;
reg [31:0] rs2 = 32'd0;
reg [31:0] \rs2$next ;
wire [4:0] shamt;
input slow_clk;
wire slow_clk;
input slow_rst;
wire slow_rst;
wire [3:0] store_wmask;
reg [31:0] takeBranch;
reg [31:0] x0 = 32'd0;
reg [31:0] \x0$next ;
reg [31:0] x1 = 32'd0;
reg [31:0] \x1$next ;
reg [31:0] x10 = 32'd0;
reg [31:0] \x10$1255 = 32'd0;
reg [31:0] \x10$1255$next ;
reg [31:0] \x10$next ;
reg [31:0] x11 = 32'd0;
reg [31:0] \x11$next ;
reg [31:0] x12 = 32'd0;
reg [31:0] \x12$next ;
reg [31:0] x13 = 32'd0;
reg [31:0] \x13$next ;
reg [31:0] x14 = 32'd0;
reg [31:0] \x14$next ;
reg [31:0] x15 = 32'd0;
reg [31:0] \x15$next ;
reg [31:0] x16 = 32'd0;
reg [31:0] \x16$next ;
reg [31:0] x17 = 32'd0;
reg [31:0] \x17$next ;
reg [31:0] x18 = 32'd0;
reg [31:0] \x18$next ;
reg [31:0] x19 = 32'd0;
reg [31:0] \x19$next ;
reg [31:0] x2 = 32'd0;
reg [31:0] \x2$next ;
reg [31:0] x20 = 32'd0;
reg [31:0] \x20$next ;
reg [31:0] x21 = 32'd0;
reg [31:0] \x21$next ;
reg [31:0] x22 = 32'd0;
reg [31:0] \x22$next ;
reg [31:0] x23 = 32'd0;
reg [31:0] \x23$next ;
reg [31:0] x24 = 32'd0;
reg [31:0] \x24$next ;
reg [31:0] x25 = 32'd0;
reg [31:0] \x25$next ;
reg [31:0] x26 = 32'd0;
reg [31:0] \x26$next ;
reg [31:0] x27 = 32'd0;
reg [31:0] \x27$next ;
reg [31:0] x28 = 32'd0;
reg [31:0] \x28$next ;
reg [31:0] x29 = 32'd0;
reg [31:0] \x29$next ;
reg [31:0] x3 = 32'd0;
reg [31:0] \x3$next ;
reg [31:0] x30 = 32'd0;
reg [31:0] \x30$next ;
reg [31:0] x31 = 32'd0;
reg [31:0] \x31$next ;
reg [31:0] x4 = 32'd0;
reg [31:0] \x4$next ;
reg [31:0] x5 = 32'd0;
reg [31:0] \x5$next ;
reg [31:0] x6 = 32'd0;
reg [31:0] \x6$next ;
reg [31:0] x7 = 32'd0;
reg [31:0] \x7$next ;
reg [31:0] x8 = 32'd0;
reg [31:0] \x8$next ;
reg [31:0] x9 = 32'd0;
reg [31:0] \x9$next ;
assign \$9 = instr[6:0] == 7'h6f;
assign \$999 = isJAL | isJALR;
assign \$998 = \$999 ? \$980 : \$996 ;
assign \$1003 = pc + 3'h4;
assign \$1005 = + Uimm;
assign \$1007 = instr[4] ? Uimm : Bimm;
assign \$100 = instr[30] & aluIn1[31];
assign \$1009 = instr[3] ? Jimm : \$1007 ;
assign \$1011 = pc + \$1009 ;
assign \$1014 = isLoad ? loadData : aluOut;
assign \$1013 = + \$1014 ;
assign \$1017 = isAUIPC ? \$1011 : \$1013 ;
assign \$1019 = isLUI ? \$1005 : \$1017 ;
assign \$1022 = isJAL | isJALR;
assign \$1021 = \$1022 ? \$1003 : \$1019 ;
assign \$1026 = pc + 3'h4;
assign \$1028 = + Uimm;
assign \$102 = $signed({ \$100 , \$96 }) >>> aluIn2[4:0];
assign \$1030 = instr[4] ? Uimm : Bimm;
assign \$1032 = instr[3] ? Jimm : \$1030 ;
assign \$1034 = pc + \$1032 ;
assign \$1037 = isLoad ? loadData : aluOut;
assign \$1036 = + \$1037 ;
assign \$1040 = isAUIPC ? \$1034 : \$1036 ;
assign \$1042 = isLUI ? \$1028 : \$1040 ;
assign \$1045 = isJAL | isJALR;
assign \$1044 = \$1045 ? \$1026 : \$1042 ;
assign \$1049 = pc + 3'h4;
assign \$1051 = + Uimm;
assign \$1053 = instr[4] ? Uimm : Bimm;
assign \$1055 = instr[3] ? Jimm : \$1053 ;
assign \$1057 = pc + \$1055 ;
assign \$1060 = isLoad ? loadData : aluOut;
assign \$1059 = + \$1060 ;
assign \$1063 = isAUIPC ? \$1057 : \$1059 ;
assign \$1065 = isLUI ? \$1051 : \$1063 ;
assign \$1068 = isJAL | isJALR;
assign \$106 = instr[14:12] == 1'h1;
assign \$1067 = \$1068 ? \$1049 : \$1065 ;
assign \$1072 = pc + 3'h4;
assign \$1074 = + Uimm;
assign \$1076 = instr[4] ? Uimm : Bimm;
assign \$1078 = instr[3] ? Jimm : \$1076 ;
assign \$105 = \$106 ? { aluIn1[0], aluIn1[1], aluIn1[2], aluIn1[3], aluIn1[4], aluIn1[5], aluIn1[6], aluIn1[7], aluIn1[8], aluIn1[9], aluIn1[10], aluIn1[11], aluIn1[12], aluIn1[13], aluIn1[14], aluIn1[15], aluIn1[16], aluIn1[17], aluIn1[18], aluIn1[19], aluIn1[20], aluIn1[21], aluIn1[22], aluIn1[23], aluIn1[24], aluIn1[25], aluIn1[26], aluIn1[27], aluIn1[28], aluIn1[29], aluIn1[30], aluIn1[31] } : aluIn1;
assign \$1080 = pc + \$1078 ;
assign \$1083 = isLoad ? loadData : aluOut;
assign \$1082 = + \$1083 ;
assign \$1086 = isAUIPC ? \$1080 : \$1082 ;
assign \$1088 = isLUI ? \$1074 : \$1086 ;
assign \$1091 = isJAL | isJALR;
assign \$1090 = \$1091 ? \$1072 : \$1088 ;
assign \$1095 = pc + 3'h4;
assign \$1097 = + Uimm;
assign \$109 = instr[30] & aluIn1[31];
assign \$1099 = instr[4] ? Uimm : Bimm;
assign \$1101 = instr[3] ? Jimm : \$1099 ;
assign \$1103 = pc + \$1101 ;
assign \$1106 = isLoad ? loadData : aluOut;
assign \$1105 = + \$1106 ;
assign \$1109 = isAUIPC ? \$1103 : \$1105 ;
assign \$1111 = isLUI ? \$1097 : \$1109 ;
assign \$1114 = isJAL | isJALR;
assign \$1113 = \$1114 ? \$1095 : \$1111 ;
assign \$1118 = pc + 3'h4;
assign \$111 = $signed({ \$109 , \$105 }) >>> aluIn2[4:0];
assign \$1120 = + Uimm;
assign \$1122 = instr[4] ? Uimm : Bimm;
assign \$1124 = instr[3] ? Jimm : \$1122 ;
assign \$1126 = pc + \$1124 ;
assign \$1129 = isLoad ? loadData : aluOut;
assign \$1128 = + \$1129 ;
assign \$1132 = isAUIPC ? \$1126 : \$1128 ;
assign \$1134 = isLUI ? \$1120 : \$1132 ;
assign \$1137 = isJAL | isJALR;
assign \$1136 = \$1137 ? \$1118 : \$1134 ;
assign \$1141 = pc + 3'h4;
assign \$1143 = + Uimm;
assign \$1145 = instr[4] ? Uimm : Bimm;
assign \$1147 = instr[3] ? Jimm : \$1145 ;
assign \$1149 = pc + \$1147 ;
assign \$1152 = isLoad ? loadData : aluOut;
assign \$1151 = + \$1152 ;
assign \$1155 = isAUIPC ? \$1149 : \$1151 ;
assign \$1157 = isLUI ? \$1143 : \$1155 ;
assign \$115 = instr[14:12] == 1'h1;
assign \$1160 = isJAL | isJALR;
assign \$1159 = \$1160 ? \$1141 : \$1157 ;
assign \$1164 = pc + 3'h4;
assign \$1166 = + Uimm;
assign \$1168 = instr[4] ? Uimm : Bimm;
assign \$114 = \$115 ? { aluIn1[0], aluIn1[1], aluIn1[2], aluIn1[3], aluIn1[4], aluIn1[5], aluIn1[6], aluIn1[7], aluIn1[8], aluIn1[9], aluIn1[10], aluIn1[11], aluIn1[12], aluIn1[13], aluIn1[14], aluIn1[15], aluIn1[16], aluIn1[17], aluIn1[18], aluIn1[19], aluIn1[20], aluIn1[21], aluIn1[22], aluIn1[23], aluIn1[24], aluIn1[25], aluIn1[26], aluIn1[27], aluIn1[28], aluIn1[29], aluIn1[30], aluIn1[31] } : aluIn1;
assign \$1170 = instr[3] ? Jimm : \$1168 ;
assign \$1172 = pc + \$1170 ;
assign \$1175 = isLoad ? loadData : aluOut;
assign \$1174 = + \$1175 ;
assign \$1178 = isAUIPC ? \$1172 : \$1174 ;
assign \$1180 = isLUI ? \$1166 : \$1178 ;
assign \$1183 = isJAL | isJALR;
assign \$1182 = \$1183 ? \$1164 : \$1180 ;
assign \$1187 = pc + 3'h4;
assign \$118 = instr[30] & aluIn1[31];
assign \$1189 = + Uimm;
assign \$1191 = instr[4] ? Uimm : Bimm;
assign \$1193 = instr[3] ? Jimm : \$1191 ;
assign \$1195 = pc + \$1193 ;
assign \$1198 = isLoad ? loadData : aluOut;
assign \$11 = instr[6:0] == 5'h17;
assign \$1197 = + \$1198 ;
assign \$1201 = isAUIPC ? \$1195 : \$1197 ;
assign \$1203 = isLUI ? \$1189 : \$1201 ;
assign \$1206 = isJAL | isJALR;
assign \$1205 = \$1206 ? \$1187 : \$1203 ;
assign \$120 = $signed({ \$118 , \$114 }) >>> aluIn2[4:0];
assign \$1210 = pc + 3'h4;
assign \$1212 = + Uimm;
assign \$1214 = instr[4] ? Uimm : Bimm;
assign \$1216 = instr[3] ? Jimm : \$1214 ;
assign \$1218 = pc + \$1216 ;
assign \$1221 = isLoad ? loadData : aluOut;
assign \$1220 = + \$1221 ;
assign \$1224 = isAUIPC ? \$1218 : \$1220 ;
assign \$1226 = isLUI ? \$1212 : \$1224 ;
assign \$1229 = isJAL | isJALR;
assign \$1228 = \$1229 ? \$1210 : \$1226 ;
assign \$1233 = pc + 3'h4;
assign \$1235 = + Uimm;
assign \$1237 = instr[4] ? Uimm : Bimm;
assign \$1239 = instr[3] ? Jimm : \$1237 ;
assign \$1241 = pc + \$1239 ;
assign \$1244 = isLoad ? loadData : aluOut;
assign \$1243 = + \$1244 ;
assign \$1247 = isAUIPC ? \$1241 : \$1243 ;
assign \$124 = instr[14:12] == 1'h1;
assign \$1249 = isLUI ? \$1235 : \$1247 ;
assign \$1252 = isJAL | isJALR;
assign \$1251 = \$1252 ? \$1233 : \$1249 ;
assign \$1256 = fsm_state == 2'h3;
assign \$1258 = ~ isBranch;
assign \$123 = \$124 ? { aluIn1[0], aluIn1[1], aluIn1[2], aluIn1[3], aluIn1[4], aluIn1[5], aluIn1[6], aluIn1[7], aluIn1[8], aluIn1[9], aluIn1[10], aluIn1[11], aluIn1[12], aluIn1[13], aluIn1[14], aluIn1[15], aluIn1[16], aluIn1[17], aluIn1[18], aluIn1[19], aluIn1[20], aluIn1[21], aluIn1[22], aluIn1[23], aluIn1[24], aluIn1[25], aluIn1[26], aluIn1[27], aluIn1[28], aluIn1[29], aluIn1[30], aluIn1[31] } : aluIn1;
assign \$1260 = \$1256 & \$1258 ;
assign \$1262 = ~ isStore;
assign \$1264 = \$1260 & \$1262 ;
assign \$1266 = ~ isLoad;
assign \$1268 = \$1264 & \$1266 ;
assign \$1270 = fsm_state == 3'h6;
assign \$1272 = \$1268 | \$1270 ;
assign \$1274 = | instr[11:7];
assign \$1276 = \$1272 & \$1274 ;
assign \$1278 = instr[11:7] == 4'ha;
assign \$127 = instr[30] & aluIn1[31];
assign \$1281 = pc + 3'h4;
assign \$1283 = + Uimm;
assign \$1285 = instr[4] ? Uimm : Bimm;
assign \$1287 = instr[3] ? Jimm : \$1285 ;
assign \$1289 = pc + \$1287 ;
assign \$1292 = isLoad ? loadData : aluOut;
assign \$1291 = + \$1292 ;
assign \$1295 = isAUIPC ? \$1289 : \$1291 ;
assign \$1297 = isLUI ? \$1283 : \$1295 ;
assign \$129 = $signed({ \$127 , \$123 }) >>> aluIn2[4:0];
assign \$1300 = isJAL | isJALR;
assign \$1299 = \$1300 ? \$1281 : \$1297 ;
always @(posedge slow_clk)
fsm_state <= \fsm_state$next ;
always @(posedge slow_clk)
instr <= \instr$next ;
always @(posedge slow_clk)
rs1 <= \rs1$next ;
always @(posedge slow_clk)
rs2 <= \rs2$next ;
always @(posedge slow_clk)
pc <= \pc$next ;
always @(posedge slow_clk)
x0 <= \x0$next ;
always @(posedge slow_clk)
x1 <= \x1$next ;
always @(posedge slow_clk)
x2 <= \x2$next ;
always @(posedge slow_clk)
x3 <= \x3$next ;
always @(posedge slow_clk)
x4 <= \x4$next ;
always @(posedge slow_clk)
x5 <= \x5$next ;
always @(posedge slow_clk)
x6 <= \x6$next ;
always @(posedge slow_clk)
x7 <= \x7$next ;
always @(posedge slow_clk)
x8 <= \x8$next ;
always @(posedge slow_clk)
x9 <= \x9$next ;
always @(posedge slow_clk)
x10 <= \x10$next ;
always @(posedge slow_clk)
x11 <= \x11$next ;
always @(posedge slow_clk)
x12 <= \x12$next ;
always @(posedge slow_clk)
x13 <= \x13$next ;
always @(posedge slow_clk)
x14 <= \x14$next ;
always @(posedge slow_clk)
x15 <= \x15$next ;
always @(posedge slow_clk)
x16 <= \x16$next ;
always @(posedge slow_clk)
x17 <= \x17$next ;
always @(posedge slow_clk)
x18 <= \x18$next ;
always @(posedge slow_clk)
x19 <= \x19$next ;
always @(posedge slow_clk)
x20 <= \x20$next ;
always @(posedge slow_clk)
x21 <= \x21$next ;
always @(posedge slow_clk)
x22 <= \x22$next ;
always @(posedge slow_clk)
x23 <= \x23$next ;
always @(posedge slow_clk)
x24 <= \x24$next ;
always @(posedge slow_clk)
x25 <= \x25$next ;
always @(posedge slow_clk)
x26 <= \x26$next ;
always @(posedge slow_clk)
x27 <= \x27$next ;
always @(posedge slow_clk)
x28 <= \x28$next ;
always @(posedge slow_clk)
x29 <= \x29$next ;
always @(posedge slow_clk)
x30 <= \x30$next ;
always @(posedge slow_clk)
x31 <= \x31$next ;
assign \$133 = instr[14:12] == 1'h1;
always @(posedge slow_clk)
\x10$1255 <= \x10$1255$next ;
assign \$132 = \$133 ? { aluIn1[0], aluIn1[1], aluIn1[2], aluIn1[3], aluIn1[4], aluIn1[5], aluIn1[6], aluIn1[7], aluIn1[8], aluIn1[9], aluIn1[10], aluIn1[11], aluIn1[12], aluIn1[13], aluIn1[14], aluIn1[15], aluIn1[16], aluIn1[17], aluIn1[18], aluIn1[19], aluIn1[20], aluIn1[21], aluIn1[22], aluIn1[23], aluIn1[24], aluIn1[25], aluIn1[26], aluIn1[27], aluIn1[28], aluIn1[29], aluIn1[30], aluIn1[31] } : aluIn1;
assign \$136 = instr[30] & aluIn1[31];
assign \$138 = $signed({ \$136 , \$132 }) >>> aluIn2[4:0];
assign \$13 = instr[6:0] == 6'h37;
assign \$142 = instr[14:12] == 1'h1;
assign \$141 = \$142 ? { aluIn1[0], aluIn1[1], aluIn1[2], aluIn1[3], aluIn1[4], aluIn1[5], aluIn1[6], aluIn1[7], aluIn1[8], aluIn1[9], aluIn1[10], aluIn1[11], aluIn1[12], aluIn1[13], aluIn1[14], aluIn1[15], aluIn1[16], aluIn1[17], aluIn1[18], aluIn1[19], aluIn1[20], aluIn1[21], aluIn1[22], aluIn1[23], aluIn1[24], aluIn1[25], aluIn1[26], aluIn1[27], aluIn1[28], aluIn1[29], aluIn1[30], aluIn1[31] } : aluIn1;
assign \$145 = instr[30] & aluIn1[31];
assign \$147 = $signed({ \$145 , \$141 }) >>> aluIn2[4:0];
assign \$151 = instr[14:12] == 1'h1;
assign \$150 = \$151 ? { aluIn1[0], aluIn1[1], aluIn1[2], aluIn1[3], aluIn1[4], aluIn1[5], aluIn1[6], aluIn1[7], aluIn1[8], aluIn1[9], aluIn1[10], aluIn1[11], aluIn1[12], aluIn1[13], aluIn1[14], aluIn1[15], aluIn1[16], aluIn1[17], aluIn1[18], aluIn1[19], aluIn1[20], aluIn1[21], aluIn1[22], aluIn1[23], aluIn1[24], aluIn1[25], aluIn1[26], aluIn1[27], aluIn1[28], aluIn1[29], aluIn1[30], aluIn1[31] } : aluIn1;
assign \$154 = instr[30] & aluIn1[31];
assign \$156 = $signed({ \$154 , \$150 }) >>> aluIn2[4:0];
assign \$15 = instr[6:0] == 2'h3;
assign \$160 = instr[14:12] == 1'h1;
assign \$159 = \$160 ? { aluIn1[0], aluIn1[1], aluIn1[2], aluIn1[3], aluIn1[4], aluIn1[5], aluIn1[6], aluIn1[7], aluIn1[8], aluIn1[9], aluIn1[10], aluIn1[11], aluIn1[12], aluIn1[13], aluIn1[14], aluIn1[15], aluIn1[16], aluIn1[17], aluIn1[18], aluIn1[19], aluIn1[20], aluIn1[21], aluIn1[22], aluIn1[23], aluIn1[24], aluIn1[25], aluIn1[26], aluIn1[27], aluIn1[28], aluIn1[29], aluIn1[30], aluIn1[31] } : aluIn1;
assign \$163 = instr[30] & aluIn1[31];
assign \$165 = $signed({ \$163 , \$159 }) >>> aluIn2[4:0];
assign \$169 = instr[14:12] == 1'h1;
assign \$168 = \$169 ? { aluIn1[0], aluIn1[1], aluIn1[2], aluIn1[3], aluIn1[4], aluIn1[5], aluIn1[6], aluIn1[7], aluIn1[8], aluIn1[9], aluIn1[10], aluIn1[11], aluIn1[12], aluIn1[13], aluIn1[14], aluIn1[15], aluIn1[16], aluIn1[17], aluIn1[18], aluIn1[19], aluIn1[20], aluIn1[21], aluIn1[22], aluIn1[23], aluIn1[24], aluIn1[25], aluIn1[26], aluIn1[27], aluIn1[28], aluIn1[29], aluIn1[30], aluIn1[31] } : aluIn1;
assign \$172 = instr[30] & aluIn1[31];
assign \$174 = $signed({ \$172 , \$168 }) >>> aluIn2[4:0];
assign \$178 = instr[14:12] == 1'h1;
assign \$17 = instr[6:0] == 6'h23;
assign \$177 = \$178 ? { aluIn1[0], aluIn1[1], aluIn1[2], aluIn1[3], aluIn1[4], aluIn1[5], aluIn1[6], aluIn1[7], aluIn1[8], aluIn1[9], aluIn1[10], aluIn1[11], aluIn1[12], aluIn1[13], aluIn1[14], aluIn1[15], aluIn1[16], aluIn1[17], aluIn1[18], aluIn1[19], aluIn1[20], aluIn1[21], aluIn1[22], aluIn1[23], aluIn1[24], aluIn1[25], aluIn1[26], aluIn1[27], aluIn1[28], aluIn1[29], aluIn1[30], aluIn1[31] } : aluIn1;
assign \$181 = instr[30] & aluIn1[31];
assign \$183 = $signed({ \$181 , \$177 }) >>> aluIn2[4:0];
assign \$187 = instr[14:12] == 1'h1;
assign \$186 = \$187 ? { aluIn1[0], aluIn1[1], aluIn1[2], aluIn1[3], aluIn1[4], aluIn1[5], aluIn1[6], aluIn1[7], aluIn1[8], aluIn1[9], aluIn1[10], aluIn1[11], aluIn1[12], aluIn1[13], aluIn1[14], aluIn1[15], aluIn1[16], aluIn1[17], aluIn1[18], aluIn1[19], aluIn1[20], aluIn1[21], aluIn1[22], aluIn1[23], aluIn1[24], aluIn1[25], aluIn1[26], aluIn1[27], aluIn1[28], aluIn1[29], aluIn1[30], aluIn1[31] } : aluIn1;
assign \$190 = instr[30] & aluIn1[31];
assign \$192 = $signed({ \$190 , \$186 }) >>> aluIn2[4:0];
assign \$196 = instr[14:12] == 1'h1;
assign \$195 = \$196 ? { aluIn1[0], aluIn1[1], aluIn1[2], aluIn1[3], aluIn1[4], aluIn1[5], aluIn1[6], aluIn1[7], aluIn1[8], aluIn1[9], aluIn1[10], aluIn1[11], aluIn1[12], aluIn1[13], aluIn1[14], aluIn1[15], aluIn1[16], aluIn1[17], aluIn1[18], aluIn1[19], aluIn1[20], aluIn1[21], aluIn1[22], aluIn1[23], aluIn1[24], aluIn1[25], aluIn1[26], aluIn1[27], aluIn1[28], aluIn1[29], aluIn1[30], aluIn1[31] } : aluIn1;
assign \$1 = instr[6:0] == 6'h33;
assign \$19 = instr[6:0] == 7'h73;
assign \$199 = instr[30] & aluIn1[31];
assign \$201 = $signed({ \$199 , \$195 }) >>> aluIn2[4:0];
assign \$205 = instr[14:12] == 1'h1;
assign \$204 = \$205 ? { aluIn1[0], aluIn1[1], aluIn1[2], aluIn1[3], aluIn1[4], aluIn1[5], aluIn1[6], aluIn1[7], aluIn1[8], aluIn1[9], aluIn1[10], aluIn1[11], aluIn1[12], aluIn1[13], aluIn1[14], aluIn1[15], aluIn1[16], aluIn1[17], aluIn1[18], aluIn1[19], aluIn1[20], aluIn1[21], aluIn1[22], aluIn1[23], aluIn1[24], aluIn1[25], aluIn1[26], aluIn1[27], aluIn1[28], aluIn1[29], aluIn1[30], aluIn1[31] } : aluIn1;
assign \$208 = instr[30] & aluIn1[31];
assign \$210 = $signed({ \$208 , \$204 }) >>> aluIn2[4:0];
assign \$214 = instr[14:12] == 1'h1;
assign \$213 = \$214 ? { aluIn1[0], aluIn1[1], aluIn1[2], aluIn1[3], aluIn1[4], aluIn1[5], aluIn1[6], aluIn1[7], aluIn1[8], aluIn1[9], aluIn1[10], aluIn1[11], aluIn1[12], aluIn1[13], aluIn1[14], aluIn1[15], aluIn1[16], aluIn1[17], aluIn1[18], aluIn1[19], aluIn1[20], aluIn1[21], aluIn1[22], aluIn1[23], aluIn1[24], aluIn1[25], aluIn1[26], aluIn1[27], aluIn1[28], aluIn1[29], aluIn1[30], aluIn1[31] } : aluIn1;
assign \$217 = instr[30] & aluIn1[31];
assign \$219 = $signed({ \$217 , \$213 }) >>> aluIn2[4:0];
assign \$223 = instr[14:12] == 1'h1;
assign \$222 = \$223 ? { aluIn1[0], aluIn1[1], aluIn1[2], aluIn1[3], aluIn1[4], aluIn1[5], aluIn1[6], aluIn1[7], aluIn1[8], aluIn1[9], aluIn1[10], aluIn1[11], aluIn1[12], aluIn1[13], aluIn1[14], aluIn1[15], aluIn1[16], aluIn1[17], aluIn1[18], aluIn1[19], aluIn1[20], aluIn1[21], aluIn1[22], aluIn1[23], aluIn1[24], aluIn1[25], aluIn1[26], aluIn1[27], aluIn1[28], aluIn1[29], aluIn1[30], aluIn1[31] } : aluIn1;
assign \$226 = instr[30] & aluIn1[31];
assign \$228 = $signed({ \$226 , \$222 }) >>> aluIn2[4:0];
assign \$22 = isALUreg | isBranch;
assign \$232 = instr[14:12] == 1'h1;
assign \$231 = \$232 ? { aluIn1[0], aluIn1[1], aluIn1[2], aluIn1[3], aluIn1[4], aluIn1[5], aluIn1[6], aluIn1[7], aluIn1[8], aluIn1[9], aluIn1[10], aluIn1[11], aluIn1[12], aluIn1[13], aluIn1[14], aluIn1[15], aluIn1[16], aluIn1[17], aluIn1[18], aluIn1[19], aluIn1[20], aluIn1[21], aluIn1[22], aluIn1[23], aluIn1[24], aluIn1[25], aluIn1[26], aluIn1[27], aluIn1[28], aluIn1[29], aluIn1[30], aluIn1[31] } : aluIn1;
assign \$235 = instr[30] & aluIn1[31];
assign \$237 = $signed({ \$235 , \$231 }) >>> aluIn2[4:0];
assign \$21 = \$22 ? rs2 : Iimm;
assign \$241 = instr[14:12] == 1'h1;
assign \$240 = \$241 ? { aluIn1[0], aluIn1[1], aluIn1[2], aluIn1[3], aluIn1[4], aluIn1[5], aluIn1[6], aluIn1[7], aluIn1[8], aluIn1[9], aluIn1[10], aluIn1[11], aluIn1[12], aluIn1[13], aluIn1[14], aluIn1[15], aluIn1[16], aluIn1[17], aluIn1[18], aluIn1[19], aluIn1[20], aluIn1[21], aluIn1[22], aluIn1[23], aluIn1[24], aluIn1[25], aluIn1[26], aluIn1[27], aluIn1[28], aluIn1[29], aluIn1[30], aluIn1[31] } : aluIn1;
assign \$244 = instr[30] & aluIn1[31];
assign \$246 = $signed({ \$244 , \$240 }) >>> aluIn2[4:0];
assign \$250 = instr[14:12] == 1'h1;
assign \$249 = \$250 ? { aluIn1[0], aluIn1[1], aluIn1[2], aluIn1[3], aluIn1[4], aluIn1[5], aluIn1[6], aluIn1[7], aluIn1[8], aluIn1[9], aluIn1[10], aluIn1[11], aluIn1[12], aluIn1[13], aluIn1[14], aluIn1[15], aluIn1[16], aluIn1[17], aluIn1[18], aluIn1[19], aluIn1[20], aluIn1[21], aluIn1[22], aluIn1[23], aluIn1[24], aluIn1[25], aluIn1[26], aluIn1[27], aluIn1[28], aluIn1[29], aluIn1[30], aluIn1[31] } : aluIn1;
assign \$253 = instr[30] & aluIn1[31];
assign \$255 = $signed({ \$253 , \$249 }) >>> aluIn2[4:0];
assign \$25 = isALUreg ? rs2[4:0] : instr[24:20];
assign \$259 = instr[14:12] == 1'h1;
assign \$258 = \$259 ? { aluIn1[0], aluIn1[1], aluIn1[2], aluIn1[3], aluIn1[4], aluIn1[5], aluIn1[6], aluIn1[7], aluIn1[8], aluIn1[9], aluIn1[10], aluIn1[11], aluIn1[12], aluIn1[13], aluIn1[14], aluIn1[15], aluIn1[16], aluIn1[17], aluIn1[18], aluIn1[19], aluIn1[20], aluIn1[21], aluIn1[22], aluIn1[23], aluIn1[24], aluIn1[25], aluIn1[26], aluIn1[27], aluIn1[28], aluIn1[29], aluIn1[30], aluIn1[31] } : aluIn1;
assign \$262 = instr[30] & aluIn1[31];
assign \$264 = $signed({ \$262 , \$258 }) >>> aluIn2[4:0];
assign \$268 = instr[14:12] == 1'h1;
assign \$267 = \$268 ? { aluIn1[0], aluIn1[1], aluIn1[2], aluIn1[3], aluIn1[4], aluIn1[5], aluIn1[6], aluIn1[7], aluIn1[8], aluIn1[9], aluIn1[10], aluIn1[11], aluIn1[12], aluIn1[13], aluIn1[14], aluIn1[15], aluIn1[16], aluIn1[17], aluIn1[18], aluIn1[19], aluIn1[20], aluIn1[21], aluIn1[22], aluIn1[23], aluIn1[24], aluIn1[25], aluIn1[26], aluIn1[27], aluIn1[28], aluIn1[29], aluIn1[30], aluIn1[31] } : aluIn1;
assign \$271 = instr[30] & aluIn1[31];
assign \$273 = $signed({ \$271 , \$267 }) >>> aluIn2[4:0];
assign \$277 = instr[14:12] == 1'h1;
assign \$276 = \$277 ? { aluIn1[0], aluIn1[1], aluIn1[2], aluIn1[3], aluIn1[4], aluIn1[5], aluIn1[6], aluIn1[7], aluIn1[8], aluIn1[9], aluIn1[10], aluIn1[11], aluIn1[12], aluIn1[13], aluIn1[14], aluIn1[15], aluIn1[16], aluIn1[17], aluIn1[18], aluIn1[19], aluIn1[20], aluIn1[21], aluIn1[22], aluIn1[23], aluIn1[24], aluIn1[25], aluIn1[26], aluIn1[27], aluIn1[28], aluIn1[29], aluIn1[30], aluIn1[31] } : aluIn1;
assign \$280 = instr[30] & aluIn1[31];
assign \$282 = $signed({ \$280 , \$276 }) >>> aluIn2[4:0];
assign \$286 = instr[14:12] == 1'h1;
assign \$285 = \$286 ? { aluIn1[0], aluIn1[1], aluIn1[2], aluIn1[3], aluIn1[4], aluIn1[5], aluIn1[6], aluIn1[7], aluIn1[8], aluIn1[9], aluIn1[10], aluIn1[11], aluIn1[12], aluIn1[13], aluIn1[14], aluIn1[15], aluIn1[16], aluIn1[17], aluIn1[18], aluIn1[19], aluIn1[20], aluIn1[21], aluIn1[22], aluIn1[23], aluIn1[24], aluIn1[25], aluIn1[26], aluIn1[27], aluIn1[28], aluIn1[29], aluIn1[30], aluIn1[31] } : aluIn1;
assign \$28 = ~ aluIn2;
assign \$289 = instr[30] & aluIn1[31];
assign \$291 = $signed({ \$289 , \$285 }) >>> aluIn2[4:0];
assign \$295 = instr[14:12] == 1'h1;
assign \$294 = \$295 ? { aluIn1[0], aluIn1[1], aluIn1[2], aluIn1[3], aluIn1[4], aluIn1[5], aluIn1[6], aluIn1[7], aluIn1[8], aluIn1[9], aluIn1[10], aluIn1[11], aluIn1[12], aluIn1[13], aluIn1[14], aluIn1[15], aluIn1[16], aluIn1[17], aluIn1[18], aluIn1[19], aluIn1[20], aluIn1[21], aluIn1[22], aluIn1[23], aluIn1[24], aluIn1[25], aluIn1[26], aluIn1[27], aluIn1[28], aluIn1[29], aluIn1[30], aluIn1[31] } : aluIn1;
assign \$298 = instr[30] & aluIn1[31];
assign \$300 = $signed({ \$298 , \$294 }) >>> aluIn2[4:0];
assign \$304 = instr[14:12] == 1'h1;
assign \$303 = \$304 ? { aluIn1[0], aluIn1[1], aluIn1[2], aluIn1[3], aluIn1[4], aluIn1[5], aluIn1[6], aluIn1[7], aluIn1[8], aluIn1[9], aluIn1[10], aluIn1[11], aluIn1[12], aluIn1[13], aluIn1[14], aluIn1[15], aluIn1[16], aluIn1[17], aluIn1[18], aluIn1[19], aluIn1[20], aluIn1[21], aluIn1[22], aluIn1[23], aluIn1[24], aluIn1[25], aluIn1[26], aluIn1[27], aluIn1[28], aluIn1[29], aluIn1[30], aluIn1[31] } : aluIn1;
assign \$307 = instr[30] & aluIn1[31];
assign \$30 = { 1'h1, \$28 } + { 1'h0, aluIn1 };
assign \$309 = $signed({ \$307 , \$303 }) >>> aluIn2[4:0];
assign \$313 = instr[14:12] == 1'h1;
assign \$312 = \$313 ? { aluIn1[0], aluIn1[1], aluIn1[2], aluIn1[3], aluIn1[4], aluIn1[5], aluIn1[6], aluIn1[7], aluIn1[8], aluIn1[9], aluIn1[10], aluIn1[11], aluIn1[12], aluIn1[13], aluIn1[14], aluIn1[15], aluIn1[16], aluIn1[17], aluIn1[18], aluIn1[19], aluIn1[20], aluIn1[21], aluIn1[22], aluIn1[23], aluIn1[24], aluIn1[25], aluIn1[26], aluIn1[27], aluIn1[28], aluIn1[29], aluIn1[30], aluIn1[31] } : aluIn1;
assign \$316 = instr[30] & aluIn1[31];
assign \$318 = $signed({ \$316 , \$312 }) >>> aluIn2[4:0];
assign \$322 = instr[14:12] == 1'h1;
assign \$321 = \$322 ? { aluIn1[0], aluIn1[1], aluIn1[2], aluIn1[3], aluIn1[4], aluIn1[5], aluIn1[6], aluIn1[7], aluIn1[8], aluIn1[9], aluIn1[10], aluIn1[11], aluIn1[12], aluIn1[13], aluIn1[14], aluIn1[15], aluIn1[16], aluIn1[17], aluIn1[18], aluIn1[19], aluIn1[20], aluIn1[21], aluIn1[22], aluIn1[23], aluIn1[24], aluIn1[25], aluIn1[26], aluIn1[27], aluIn1[28], aluIn1[29], aluIn1[30], aluIn1[31] } : aluIn1;
assign \$325 = instr[30] & aluIn1[31];
assign \$327 = $signed({ \$325 , \$321 }) >>> aluIn2[4:0];
assign \$32 = \$30 + 1'h1;
assign \$331 = aluIn1[31] ^ aluIn2[31];
assign \$330 = \$331 ? aluIn1[31] : aluMinus[32];
assign \$329 = + \$330 ;
assign \$335 = + aluMinus[32];
assign \$337 = aluIn1 ^ aluIn2;
assign \$341 = instr[14:12] == 1'h1;
assign \$340 = \$341 ? { aluIn1[0], aluIn1[1], aluIn1[2], aluIn1[3], aluIn1[4], aluIn1[5], aluIn1[6], aluIn1[7], aluIn1[8], aluIn1[9], aluIn1[10], aluIn1[11], aluIn1[12], aluIn1[13], aluIn1[14], aluIn1[15], aluIn1[16], aluIn1[17], aluIn1[18], aluIn1[19], aluIn1[20], aluIn1[21], aluIn1[22], aluIn1[23], aluIn1[24], aluIn1[25], aluIn1[26], aluIn1[27], aluIn1[28], aluIn1[29], aluIn1[30], aluIn1[31] } : aluIn1;
assign \$344 = instr[30] & aluIn1[31];
assign \$346 = $signed({ \$344 , \$340 }) >>> aluIn2[4:0];
assign \$348 = aluIn1 | aluIn2;
assign \$350 = aluIn1 & aluIn2;
assign \$353 = ! aluMinus[31:0];
assign \$352 = + \$353 ;
assign \$358 = ! aluMinus[31:0];
assign \$35 = aluIn1 + aluIn2;
assign \$357 = ~ \$358 ;
assign \$356 = + \$357 ;
assign \$364 = aluIn1[31] ^ aluIn2[31];
assign \$363 = \$364 ? aluIn1[31] : aluMinus[32];
assign \$362 = + \$363 ;
assign \$371 = aluIn1[31] ^ aluIn2[31];
assign \$370 = \$371 ? aluIn1[31] : aluMinus[32];
assign \$369 = ~ \$370 ;
assign \$368 = + \$369 ;
assign \$376 = + aluMinus[32];
assign \$379 = ~ aluMinus[32];
assign \$378 = + \$379 ;
assign \$382 = ~ isSystem;
assign \$385 = instr[4] ? Uimm : Bimm;
assign \$387 = instr[3] ? Jimm : \$385 ;
assign \$38 = instr[30] & instr[5];
assign \$389 = pc + \$387 ;
assign \$391 = + { aluPlus[31:1], 1'h0 };
assign \$393 = pc + 3'h4;
assign \$395 = isJALR ? \$391 : \$393 ;
assign \$3 = instr[6:0] == 5'h13;
assign \$37 = \$38 ? aluMinus[31:0] : aluPlus;
assign \$399 = isBranch & takeBranch;
assign \$401 = \$399 | isJAL;
assign \$398 = | \$401 ;
assign \$397 = \$398 ? \$389 : \$395 ;
assign \$406 = isStore ? Simm : Iimm;
assign \$408 = rs1 + \$406 ;
assign \$410 = ! instr[13:12];
assign \$412 = instr[13:12] == 2'h1;
assign \$414 = loadStoreAddr[1] ? mem_rdata[31:16] : mem_rdata[15:0];
assign \$416 = loadStoreAddr[0] ? loadHalfword[15:8] : loadHalfword[7:0];
assign \$418 = ~ instr[14];
assign \$420 = memByteAccess ? loadByte[7] : loadHalfword[15];
assign \$422 = \$418 & \$420 ;
assign \$424 = memHalfwordAccess ? { loadSign, loadSign, loadSign, loadSign, loadSign, loadSign, loadSign, loadSign, loadSign, loadSign, loadSign, loadSign, loadSign, loadSign, loadSign, loadSign, loadHalfword } : mem_rdata;
assign \$426 = memByteAccess ? { loadSign, loadSign, loadSign, loadSign, loadSign, loadSign, loadSign, loadSign, loadSign, loadSign, loadSign, loadSign, loadSign, loadSign, loadSign, loadSign, loadSign, loadSign, loadSign, loadSign, loadSign, loadSign, loadSign, loadSign, loadByte } : \$424 ;
assign \$428 = loadStoreAddr[0] ? rs2[7:0] : rs2[15:8];
assign \$430 = loadStoreAddr[1] ? rs2[7:0] : rs2[23:16];
assign \$432 = loadStoreAddr[1] ? rs2[15:8] : rs2[31:24];
assign \$434 = loadStoreAddr[0] ? rs2[7:0] : \$432 ;
assign \$436 = loadStoreAddr[0] ? 4'h8 : 4'h4;
assign \$43 = instr[14:12] == 1'h1;
assign \$439 = loadStoreAddr[0] ? 2'h2 : 2'h1;
assign \$438 = + \$439 ;
assign \$442 = loadStoreAddr[1] ? \$436 : \$438 ;
assign \$444 = loadStoreAddr[1] ? 4'hc : 4'h3;
assign \$446 = memHalfwordAccess ? \$444 : 4'hf;
assign \$448 = memByteAccess ? \$442 : \$446 ;
assign \$42 = \$43 ? { aluIn1[0], aluIn1[1], aluIn1[2], aluIn1[3], aluIn1[4], aluIn1[5], aluIn1[6], aluIn1[7], aluIn1[8], aluIn1[9], aluIn1[10], aluIn1[11], aluIn1[12], aluIn1[13], aluIn1[14], aluIn1[15], aluIn1[16], aluIn1[17], aluIn1[18], aluIn1[19], aluIn1[20], aluIn1[21], aluIn1[22], aluIn1[23], aluIn1[24], aluIn1[25], aluIn1[26], aluIn1[27], aluIn1[28], aluIn1[29], aluIn1[30], aluIn1[31] } : aluIn1;
assign \$451 = fsm_state == 1'h1;
assign \$453 = ! fsm_state;
assign \$455 = \$451 | \$453 ;
assign \$450 = \$455 ? pc : loadStoreAddr;
assign \$458 = ! fsm_state;
assign \$460 = fsm_state == 3'h4;
assign \$462 = \$458 | \$460 ;
assign \$464 = fsm_state == 3'h5;
assign \$466 = fsm_state == 3'h5;
assign \$468 = fsm_state == 3'h5;
assign \$46 = instr[30] & aluIn1[31];
assign \$470 = fsm_state == 3'h5;
assign \$472 = { \$464 , \$466 , \$468 , \$470 } & store_wmask;
assign \$474 = fsm_state == 2'h3;
assign \$476 = ~ isBranch;
assign \$478 = \$474 & \$476 ;
assign \$480 = ~ isStore;
assign \$482 = \$478 & \$480 ;
assign \$484 = ~ isLoad;
assign \$486 = \$482 & \$484 ;
assign \$488 = fsm_state == 3'h6;
assign \$48 = $signed({ \$46 , \$42 }) >>> aluIn2[4:0];
assign \$490 = \$486 | \$488 ;
assign \$492 = | instr[11:7];
assign \$494 = \$490 & \$492 ;
assign \$497 = pc + 3'h4;
assign \$499 = + Uimm;
assign \$501 = instr[4] ? Uimm : Bimm;
assign \$503 = instr[3] ? Jimm : \$501 ;
assign \$505 = pc + \$503 ;
assign \$508 = isLoad ? loadData : aluOut;
assign \$507 = + \$508 ;
assign \$511 = isAUIPC ? \$505 : \$507 ;
assign \$513 = isLUI ? \$499 : \$511 ;
assign \$516 = isJAL | isJALR;
assign \$515 = \$516 ? \$497 : \$513 ;
assign \$520 = pc + 3'h4;
assign \$522 = + Uimm;
assign \$524 = instr[4] ? Uimm : Bimm;
assign \$526 = instr[3] ? Jimm : \$524 ;
assign \$528 = pc + \$526 ;
assign \$52 = instr[14:12] == 1'h1;
assign \$531 = isLoad ? loadData : aluOut;
assign \$530 = + \$531 ;
assign \$534 = isAUIPC ? \$528 : \$530 ;
assign \$536 = isLUI ? \$522 : \$534 ;
assign \$51 = \$52 ? { aluIn1[0], aluIn1[1], aluIn1[2], aluIn1[3], aluIn1[4], aluIn1[5], aluIn1[6], aluIn1[7], aluIn1[8], aluIn1[9], aluIn1[10], aluIn1[11], aluIn1[12], aluIn1[13], aluIn1[14], aluIn1[15], aluIn1[16], aluIn1[17], aluIn1[18], aluIn1[19], aluIn1[20], aluIn1[21], aluIn1[22], aluIn1[23], aluIn1[24], aluIn1[25], aluIn1[26], aluIn1[27], aluIn1[28], aluIn1[29], aluIn1[30], aluIn1[31] } : aluIn1;
assign \$539 = isJAL | isJALR;
assign \$538 = \$539 ? \$520 : \$536 ;
assign \$543 = pc + 3'h4;
assign \$545 = + Uimm;
assign \$547 = instr[4] ? Uimm : Bimm;
assign \$549 = instr[3] ? Jimm : \$547 ;
assign \$551 = pc + \$549 ;
assign \$554 = isLoad ? loadData : aluOut;
assign \$553 = + \$554 ;
assign \$557 = isAUIPC ? \$551 : \$553 ;
assign \$55 = instr[30] & aluIn1[31];
assign \$559 = isLUI ? \$545 : \$557 ;
assign \$562 = isJAL | isJALR;
assign \$561 = \$562 ? \$543 : \$559 ;
assign \$566 = pc + 3'h4;
assign \$568 = + Uimm;
assign \$570 = instr[4] ? Uimm : Bimm;
assign \$572 = instr[3] ? Jimm : \$570 ;
assign \$574 = pc + \$572 ;
assign \$577 = isLoad ? loadData : aluOut;
assign \$576 = + \$577 ;
assign \$57 = $signed({ \$55 , \$51 }) >>> aluIn2[4:0];
assign \$580 = isAUIPC ? \$574 : \$576 ;
assign \$582 = isLUI ? \$568 : \$580 ;
assign \$585 = isJAL | isJALR;
assign \$584 = \$585 ? \$566 : \$582 ;
assign \$589 = pc + 3'h4;
assign \$591 = + Uimm;
assign \$593 = instr[4] ? Uimm : Bimm;
assign \$595 = instr[3] ? Jimm : \$593 ;
assign \$597 = pc + \$595 ;
assign \$5 = instr[6:0] == 7'h63;
assign \$600 = isLoad ? loadData : aluOut;
assign \$599 = + \$600 ;
assign \$603 = isAUIPC ? \$597 : \$599 ;
assign \$605 = isLUI ? \$591 : \$603 ;
assign \$608 = isJAL | isJALR;
assign \$607 = \$608 ? \$589 : \$605 ;
assign \$612 = pc + 3'h4;
assign \$614 = + Uimm;
assign \$616 = instr[4] ? Uimm : Bimm;
assign \$618 = instr[3] ? Jimm : \$616 ;
assign \$61 = instr[14:12] == 1'h1;
assign \$620 = pc + \$618 ;
assign \$623 = isLoad ? loadData : aluOut;
assign \$622 = + \$623 ;
assign \$626 = isAUIPC ? \$620 : \$622 ;
assign \$628 = isLUI ? \$614 : \$626 ;
assign \$60 = \$61 ? { aluIn1[0], aluIn1[1], aluIn1[2], aluIn1[3], aluIn1[4], aluIn1[5], aluIn1[6], aluIn1[7], aluIn1[8], aluIn1[9], aluIn1[10], aluIn1[11], aluIn1[12], aluIn1[13], aluIn1[14], aluIn1[15], aluIn1[16], aluIn1[17], aluIn1[18], aluIn1[19], aluIn1[20], aluIn1[21], aluIn1[22], aluIn1[23], aluIn1[24], aluIn1[25], aluIn1[26], aluIn1[27], aluIn1[28], aluIn1[29], aluIn1[30], aluIn1[31] } : aluIn1;
assign \$631 = isJAL | isJALR;
assign \$630 = \$631 ? \$612 : \$628 ;
assign \$635 = pc + 3'h4;
assign \$637 = + Uimm;
assign \$639 = instr[4] ? Uimm : Bimm;
assign \$641 = instr[3] ? Jimm : \$639 ;
assign \$643 = pc + \$641 ;
assign \$646 = isLoad ? loadData : aluOut;
assign \$645 = + \$646 ;
assign \$64 = instr[30] & aluIn1[31];
assign \$649 = isAUIPC ? \$643 : \$645 ;
assign \$651 = isLUI ? \$637 : \$649 ;
assign \$654 = isJAL | isJALR;
assign \$653 = \$654 ? \$635 : \$651 ;
assign \$658 = pc + 3'h4;
assign \$660 = + Uimm;
assign \$662 = instr[4] ? Uimm : Bimm;
assign \$664 = instr[3] ? Jimm : \$662 ;
assign \$666 = pc + \$664 ;
assign \$66 = $signed({ \$64 , \$60 }) >>> aluIn2[4:0];
assign \$669 = isLoad ? loadData : aluOut;
assign \$668 = + \$669 ;
assign \$672 = isAUIPC ? \$666 : \$668 ;
assign \$674 = isLUI ? \$660 : \$672 ;
assign \$677 = isJAL | isJALR;
assign \$676 = \$677 ? \$658 : \$674 ;
assign \$681 = pc + 3'h4;
assign \$683 = + Uimm;
assign \$685 = instr[4] ? Uimm : Bimm;
assign \$687 = instr[3] ? Jimm : \$685 ;
assign \$689 = pc + \$687 ;
assign \$692 = isLoad ? loadData : aluOut;
assign \$691 = + \$692 ;
assign \$695 = isAUIPC ? \$689 : \$691 ;
assign \$697 = isLUI ? \$683 : \$695 ;
assign \$700 = isJAL | isJALR;
assign \$699 = \$700 ? \$681 : \$697 ;
assign \$704 = pc + 3'h4;
assign \$706 = + Uimm;
assign \$708 = instr[4] ? Uimm : Bimm;
assign \$70 = instr[14:12] == 1'h1;
assign \$710 = instr[3] ? Jimm : \$708 ;
assign \$712 = pc + \$710 ;
assign \$715 = isLoad ? loadData : aluOut;
assign \$714 = + \$715 ;
assign \$718 = isAUIPC ? \$712 : \$714 ;
assign \$69 = \$70 ? { aluIn1[0], aluIn1[1], aluIn1[2], aluIn1[3], aluIn1[4], aluIn1[5], aluIn1[6], aluIn1[7], aluIn1[8], aluIn1[9], aluIn1[10], aluIn1[11], aluIn1[12], aluIn1[13], aluIn1[14], aluIn1[15], aluIn1[16], aluIn1[17], aluIn1[18], aluIn1[19], aluIn1[20], aluIn1[21], aluIn1[22], aluIn1[23], aluIn1[24], aluIn1[25], aluIn1[26], aluIn1[27], aluIn1[28], aluIn1[29], aluIn1[30], aluIn1[31] } : aluIn1;
assign \$720 = isLUI ? \$706 : \$718 ;
assign \$723 = isJAL | isJALR;
assign \$722 = \$723 ? \$704 : \$720 ;
assign \$727 = pc + 3'h4;
assign \$729 = + Uimm;
assign \$731 = instr[4] ? Uimm : Bimm;
assign \$733 = instr[3] ? Jimm : \$731 ;
assign \$735 = pc + \$733 ;
assign \$738 = isLoad ? loadData : aluOut;
assign \$73 = instr[30] & aluIn1[31];
assign \$737 = + \$738 ;
assign \$741 = isAUIPC ? \$735 : \$737 ;
assign \$743 = isLUI ? \$729 : \$741 ;
assign \$746 = isJAL | isJALR;
assign \$745 = \$746 ? \$727 : \$743 ;
assign \$750 = pc + 3'h4;
assign \$752 = + Uimm;
assign \$754 = instr[4] ? Uimm : Bimm;
assign \$756 = instr[3] ? Jimm : \$754 ;
assign \$758 = pc + \$756 ;
assign \$75 = $signed({ \$73 , \$69 }) >>> aluIn2[4:0];
assign \$761 = isLoad ? loadData : aluOut;
assign \$760 = + \$761 ;
assign \$764 = isAUIPC ? \$758 : \$760 ;
assign \$766 = isLUI ? \$752 : \$764 ;
assign \$769 = isJAL | isJALR;
assign \$768 = \$769 ? \$750 : \$766 ;
assign \$773 = pc + 3'h4;
assign \$775 = + Uimm;
assign \$777 = instr[4] ? Uimm : Bimm;
assign \$779 = instr[3] ? Jimm : \$777 ;
assign \$781 = pc + \$779 ;
assign \$784 = isLoad ? loadData : aluOut;
assign \$783 = + \$784 ;
assign \$787 = isAUIPC ? \$781 : \$783 ;
assign \$789 = isLUI ? \$775 : \$787 ;
assign \$792 = isJAL | isJALR;
assign \$791 = \$792 ? \$773 : \$789 ;
assign \$796 = pc + 3'h4;
assign \$798 = + Uimm;
assign \$7 = instr[6:0] == 7'h67;
assign \$79 = instr[14:12] == 1'h1;
assign \$800 = instr[4] ? Uimm : Bimm;
assign \$802 = instr[3] ? Jimm : \$800 ;
assign \$804 = pc + \$802 ;
assign \$807 = isLoad ? loadData : aluOut;
assign \$806 = + \$807 ;
assign \$78 = \$79 ? { aluIn1[0], aluIn1[1], aluIn1[2], aluIn1[3], aluIn1[4], aluIn1[5], aluIn1[6], aluIn1[7], aluIn1[8], aluIn1[9], aluIn1[10], aluIn1[11], aluIn1[12], aluIn1[13], aluIn1[14], aluIn1[15], aluIn1[16], aluIn1[17], aluIn1[18], aluIn1[19], aluIn1[20], aluIn1[21], aluIn1[22], aluIn1[23], aluIn1[24], aluIn1[25], aluIn1[26], aluIn1[27], aluIn1[28], aluIn1[29], aluIn1[30], aluIn1[31] } : aluIn1;
assign \$810 = isAUIPC ? \$804 : \$806 ;
assign \$812 = isLUI ? \$798 : \$810 ;
assign \$815 = isJAL | isJALR;
assign \$814 = \$815 ? \$796 : \$812 ;
assign \$819 = pc + 3'h4;
assign \$821 = + Uimm;
assign \$823 = instr[4] ? Uimm : Bimm;
assign \$825 = instr[3] ? Jimm : \$823 ;
assign \$827 = pc + \$825 ;
assign \$82 = instr[30] & aluIn1[31];
assign \$830 = isLoad ? loadData : aluOut;
assign \$829 = + \$830 ;
assign \$833 = isAUIPC ? \$827 : \$829 ;
assign \$835 = isLUI ? \$821 : \$833 ;
assign \$838 = isJAL | isJALR;
assign \$837 = \$838 ? \$819 : \$835 ;
assign \$842 = pc + 3'h4;
assign \$844 = + Uimm;
assign \$846 = instr[4] ? Uimm : Bimm;
assign \$848 = instr[3] ? Jimm : \$846 ;
assign \$84 = $signed({ \$82 , \$78 }) >>> aluIn2[4:0];
assign \$850 = pc + \$848 ;
assign \$853 = isLoad ? loadData : aluOut;
assign \$852 = + \$853 ;
assign \$856 = isAUIPC ? \$850 : \$852 ;
assign \$858 = isLUI ? \$844 : \$856 ;
assign \$861 = isJAL | isJALR;
assign \$860 = \$861 ? \$842 : \$858 ;
assign \$865 = pc + 3'h4;
assign \$867 = + Uimm;
assign \$869 = instr[4] ? Uimm : Bimm;
assign \$871 = instr[3] ? Jimm : \$869 ;
assign \$873 = pc + \$871 ;
assign \$876 = isLoad ? loadData : aluOut;
assign \$875 = + \$876 ;
assign \$879 = isAUIPC ? \$873 : \$875 ;
assign \$881 = isLUI ? \$867 : \$879 ;
assign \$884 = isJAL | isJALR;
assign \$883 = \$884 ? \$865 : \$881 ;
assign \$888 = pc + 3'h4;
assign \$88 = instr[14:12] == 1'h1;
assign \$890 = + Uimm;
assign \$892 = instr[4] ? Uimm : Bimm;
assign \$894 = instr[3] ? Jimm : \$892 ;
assign \$896 = pc + \$894 ;
assign \$87 = \$88 ? { aluIn1[0], aluIn1[1], aluIn1[2], aluIn1[3], aluIn1[4], aluIn1[5], aluIn1[6], aluIn1[7], aluIn1[8], aluIn1[9], aluIn1[10], aluIn1[11], aluIn1[12], aluIn1[13], aluIn1[14], aluIn1[15], aluIn1[16], aluIn1[17], aluIn1[18], aluIn1[19], aluIn1[20], aluIn1[21], aluIn1[22], aluIn1[23], aluIn1[24], aluIn1[25], aluIn1[26], aluIn1[27], aluIn1[28], aluIn1[29], aluIn1[30], aluIn1[31] } : aluIn1;
assign \$899 = isLoad ? loadData : aluOut;
assign \$898 = + \$899 ;
assign \$902 = isAUIPC ? \$896 : \$898 ;
assign \$904 = isLUI ? \$890 : \$902 ;
assign \$907 = isJAL | isJALR;
assign \$906 = \$907 ? \$888 : \$904 ;
assign \$911 = pc + 3'h4;
assign \$913 = + Uimm;
assign \$915 = instr[4] ? Uimm : Bimm;
assign \$917 = instr[3] ? Jimm : \$915 ;
assign \$91 = instr[30] & aluIn1[31];
assign \$919 = pc + \$917 ;
assign \$922 = isLoad ? loadData : aluOut;
assign \$921 = + \$922 ;
assign \$925 = isAUIPC ? \$919 : \$921 ;
assign \$927 = isLUI ? \$913 : \$925 ;
assign \$930 = isJAL | isJALR;
assign \$929 = \$930 ? \$911 : \$927 ;
assign \$934 = pc + 3'h4;
assign \$936 = + Uimm;
assign \$938 = instr[4] ? Uimm : Bimm;
assign \$93 = $signed({ \$91 , \$87 }) >>> aluIn2[4:0];
assign \$940 = instr[3] ? Jimm : \$938 ;
assign \$942 = pc + \$940 ;
assign \$945 = isLoad ? loadData : aluOut;
assign \$944 = + \$945 ;
assign \$948 = isAUIPC ? \$942 : \$944 ;
assign \$950 = isLUI ? \$936 : \$948 ;
assign \$953 = isJAL | isJALR;
assign \$952 = \$953 ? \$934 : \$950 ;
assign \$957 = pc + 3'h4;
assign \$959 = + Uimm;
assign \$961 = instr[4] ? Uimm : Bimm;
assign \$963 = instr[3] ? Jimm : \$961 ;
assign \$965 = pc + \$963 ;
assign \$968 = isLoad ? loadData : aluOut;
assign \$967 = + \$968 ;
assign \$971 = isAUIPC ? \$965 : \$967 ;
assign \$973 = isLUI ? \$959 : \$971 ;
assign \$976 = isJAL | isJALR;
assign \$975 = \$976 ? \$957 : \$973 ;
assign \$97 = instr[14:12] == 1'h1;
assign \$980 = pc + 3'h4;
assign \$982 = + Uimm;
assign \$984 = instr[4] ? Uimm : Bimm;
assign \$986 = instr[3] ? Jimm : \$984 ;
assign \$988 = pc + \$986 ;
assign \$96 = \$97 ? { aluIn1[0], aluIn1[1], aluIn1[2], aluIn1[3], aluIn1[4], aluIn1[5], aluIn1[6], aluIn1[7], aluIn1[8], aluIn1[9], aluIn1[10], aluIn1[11], aluIn1[12], aluIn1[13], aluIn1[14], aluIn1[15], aluIn1[16], aluIn1[17], aluIn1[18], aluIn1[19], aluIn1[20], aluIn1[21], aluIn1[22], aluIn1[23], aluIn1[24], aluIn1[25], aluIn1[26], aluIn1[27], aluIn1[28], aluIn1[29], aluIn1[30], aluIn1[31] } : aluIn1;
assign \$991 = isLoad ? loadData : aluOut;
assign \$990 = + \$991 ;
assign \$994 = isAUIPC ? \$988 : \$990 ;
assign \$996 = isLUI ? \$982 : \$994 ;
always @* begin
if (\$auto$verilog_backend.cc:2083:dump_module$1 ) begin end
(* full_case = 32'd1 *)
casez (instr[14:12])
/* src = "18_mandelbrot/cpu.py:137" */
3'h0:
aluOut = \$37 ;
/* src = "18_mandelbrot/cpu.py:140" */
3'h1:
aluOut = { \$327 [0], \$318 [1], \$309 [2], \$300 [3], \$291 [4], \$282 [5], \$273 [6], \$264 [7], \$255 [8], \$246 [9], \$237 [10], \$228 [11], \$219 [12], \$210 [13], \$201 [14], \$192 [15], \$183 [16], \$174 [17], \$165 [18], \$156 [19], \$147 [20], \$138 [21], \$129 [22], \$120 [23], \$111 [24], \$102 [25], \$93 [26], \$84 [27], \$75 [28], \$66 [29], \$57 [30], \$48 [31] };
/* src = "18_mandelbrot/cpu.py:142" */
3'h2:
aluOut = \$329 ;
/* src = "18_mandelbrot/cpu.py:144" */
3'h3:
aluOut = \$335 ;
/* src = "18_mandelbrot/cpu.py:146" */
3'h4:
aluOut = \$337 ;
/* src = "18_mandelbrot/cpu.py:148" */
3'h5:
aluOut = \$346 [31:0];
/* src = "18_mandelbrot/cpu.py:150" */
3'h6:
aluOut = \$348 ;
/* src = "18_mandelbrot/cpu.py:152" */
3'h7:
aluOut = \$350 ;
endcase
end
always @* begin
if (\$auto$verilog_backend.cc:2083:dump_module$1 ) begin end
(* full_case = 32'd1 *)
casez (instr[14:12])
/* src = "18_mandelbrot/cpu.py:156" */
3'h0:
takeBranch = \$352 ;
/* src = "18_mandelbrot/cpu.py:158" */
3'h1:
takeBranch = \$356 ;
/* src = "18_mandelbrot/cpu.py:160" */
3'h4:
takeBranch = \$362 ;
/* src = "18_mandelbrot/cpu.py:162" */
3'h5:
takeBranch = \$368 ;
/* src = "18_mandelbrot/cpu.py:164" */
3'h6:
takeBranch = \$376 ;
/* src = "18_mandelbrot/cpu.py:166" */
3'h7:
takeBranch = \$378 ;
/* src = "18_mandelbrot/cpu.py:168" */
3'h?:
takeBranch = 32'd0;
endcase
end
always @* begin
if (\$auto$verilog_backend.cc:2083:dump_module$1 ) begin end
\fsm_state$next = fsm_state;
casez (fsm_state)
/* src = "18_mandelbrot/cpu.py:185" */
/* \amaranth.decoding = "FETCH_INSTR/0" */
3'h0:
\fsm_state$next = 3'h1;
/* src = "18_mandelbrot/cpu.py:187" */
/* \amaranth.decoding = "WAIT_INSTR/1" */
3'h1:
\fsm_state$next = 3'h2;
/* src = "18_mandelbrot/cpu.py:190" */
/* \amaranth.decoding = "FETCH_REGS/2" */
3'h2:
\fsm_state$next = 3'h3;
/* src = "18_mandelbrot/cpu.py:196" */
/* \amaranth.decoding = "EXECUTE/3" */
3'h3:
(* full_case = 32'd1 *)
casez ({ isStore, isLoad })
/* src = "18_mandelbrot/cpu.py:199" */
2'b?1:
\fsm_state$next = 3'h4;
/* src = "18_mandelbrot/cpu.py:201" */
2'b1?:
\fsm_state$next = 3'h5;
/* src = "18_mandelbrot/cpu.py:203" */
default:
\fsm_state$next = 3'h0;
endcase
/* src = "18_mandelbrot/cpu.py:205" */
/* \amaranth.decoding = "LOAD/4" */
3'h4:
\fsm_state$next = 3'h6;
/* src = "18_mandelbrot/cpu.py:207" */
/* \amaranth.decoding = "WAIT_DATA/6" */
3'h6:
\fsm_state$next = 3'h0;
/* src = "18_mandelbrot/cpu.py:209" */
/* \amaranth.decoding = "STORE/5" */
3'h5:
\fsm_state$next = 3'h0;
endcase
casez (slow_rst)
1'h1:
\fsm_state$next = 3'h0;
endcase
end
always @* begin
if (\$auto$verilog_backend.cc:2083:dump_module$1 ) begin end
\instr$next = instr;
casez (fsm_state)
/* src = "18_mandelbrot/cpu.py:185" */
/* \amaranth.decoding = "FETCH_INSTR/0" */
3'h0:
/* empty */;
/* src = "18_mandelbrot/cpu.py:187" */
/* \amaranth.decoding = "WAIT_INSTR/1" */
3'h1:
\instr$next = mem_rdata;
endcase
casez (slow_rst)
1'h1:
\instr$next = 32'd51;
endcase
end
always @* begin
if (\$auto$verilog_backend.cc:2083:dump_module$1 ) begin end
\rs1$next = rs1;
casez (fsm_state)
/* src = "18_mandelbrot/cpu.py:185" */
/* \amaranth.decoding = "FETCH_INSTR/0" */
3'h0:
/* empty */;
/* src = "18_mandelbrot/cpu.py:187" */
/* \amaranth.decoding = "WAIT_INSTR/1" */
3'h1:
/* empty */;
/* src = "18_mandelbrot/cpu.py:190" */
/* \amaranth.decoding = "FETCH_REGS/2" */
3'h2:
(* full_case = 32'd1 *)
casez (instr[19:15])
5'h00:
\rs1$next = x0;
5'h01:
\rs1$next = x1;
5'h02:
\rs1$next = x2;
5'h03:
\rs1$next = x3;
5'h04:
\rs1$next = x4;
5'h05:
\rs1$next = x5;
5'h06:
\rs1$next = x6;
5'h07:
\rs1$next = x7;
5'h08:
\rs1$next = x8;
5'h09:
\rs1$next = x9;
5'h0a:
\rs1$next = x10;
5'h0b:
\rs1$next = x11;
5'h0c:
\rs1$next = x12;
5'h0d:
\rs1$next = x13;
5'h0e:
\rs1$next = x14;
5'h0f:
\rs1$next = x15;
5'h10:
\rs1$next = x16;
5'h11:
\rs1$next = x17;
5'h12:
\rs1$next = x18;
5'h13:
\rs1$next = x19;
5'h14:
\rs1$next = x20;
5'h15:
\rs1$next = x21;
5'h16:
\rs1$next = x22;
5'h17:
\rs1$next = x23;
5'h18:
\rs1$next = x24;
5'h19:
\rs1$next = x25;
5'h1a:
\rs1$next = x26;
5'h1b:
\rs1$next = x27;
5'h1c:
\rs1$next = x28;
5'h1d:
\rs1$next = x29;
5'h1e:
\rs1$next = x30;
5'h??:
\rs1$next = x31;
endcase
endcase
casez (slow_rst)
1'h1:
\rs1$next = 32'd0;
endcase
end
always @* begin
if (\$auto$verilog_backend.cc:2083:dump_module$1 ) begin end
\rs2$next = rs2;
casez (fsm_state)
/* src = "18_mandelbrot/cpu.py:185" */
/* \amaranth.decoding = "FETCH_INSTR/0" */
3'h0:
/* empty */;
/* src = "18_mandelbrot/cpu.py:187" */
/* \amaranth.decoding = "WAIT_INSTR/1" */
3'h1:
/* empty */;
/* src = "18_mandelbrot/cpu.py:190" */
/* \amaranth.decoding = "FETCH_REGS/2" */
3'h2:
(* full_case = 32'd1 *)
casez (instr[24:20])
5'h00:
\rs2$next = x0;
5'h01:
\rs2$next = x1;
5'h02:
\rs2$next = x2;
5'h03:
\rs2$next = x3;
5'h04:
\rs2$next = x4;
5'h05:
\rs2$next = x5;
5'h06:
\rs2$next = x6;
5'h07:
\rs2$next = x7;
5'h08:
\rs2$next = x8;
5'h09:
\rs2$next = x9;
5'h0a:
\rs2$next = x10;
5'h0b:
\rs2$next = x11;
5'h0c:
\rs2$next = x12;
5'h0d:
\rs2$next = x13;
5'h0e:
\rs2$next = x14;
5'h0f:
\rs2$next = x15;
5'h10:
\rs2$next = x16;
5'h11:
\rs2$next = x17;
5'h12:
\rs2$next = x18;
5'h13:
\rs2$next = x19;
5'h14:
\rs2$next = x20;
5'h15:
\rs2$next = x21;
5'h16:
\rs2$next = x22;
5'h17:
\rs2$next = x23;
5'h18:
\rs2$next = x24;
5'h19:
\rs2$next = x25;
5'h1a:
\rs2$next = x26;
5'h1b:
\rs2$next = x27;
5'h1c:
\rs2$next = x28;
5'h1d:
\rs2$next = x29;
5'h1e:
\rs2$next = x30;
5'h??:
\rs2$next = x31;
endcase
endcase
casez (slow_rst)
1'h1:
\rs2$next = 32'd0;
endcase
end
always @* begin
if (\$auto$verilog_backend.cc:2083:dump_module$1 ) begin end
\pc$next = pc;
casez (fsm_state)
/* src = "18_mandelbrot/cpu.py:185" */
/* \amaranth.decoding = "FETCH_INSTR/0" */
3'h0:
/* empty */;
/* src = "18_mandelbrot/cpu.py:187" */
/* \amaranth.decoding = "WAIT_INSTR/1" */
3'h1:
/* empty */;
/* src = "18_mandelbrot/cpu.py:190" */
/* \amaranth.decoding = "FETCH_REGS/2" */
3'h2:
/* empty */;
/* src = "18_mandelbrot/cpu.py:196" */
/* \amaranth.decoding = "EXECUTE/3" */
3'h3:
casez (\$382 )
/* src = "18_mandelbrot/cpu.py:197" */
1'h1:
\pc$next = \$397 [31:0];
endcase
endcase
casez (slow_rst)
1'h1:
\pc$next = 32'd0;
endcase
end
always @* begin
if (\$auto$verilog_backend.cc:2083:dump_module$1 ) begin end
\x0$next = x0;
\x1$next = x1;
\x2$next = x2;
\x3$next = x3;
\x4$next = x4;
\x5$next = x5;
\x6$next = x6;
\x7$next = x7;
\x8$next = x8;
\x9$next = x9;
\x10$next = x10;
\x11$next = x11;
\x12$next = x12;
\x13$next = x13;
\x14$next = x14;
\x15$next = x15;
\x16$next = x16;
\x17$next = x17;
\x18$next = x18;
\x19$next = x19;
\x20$next = x20;
\x21$next = x21;
\x22$next = x22;
\x23$next = x23;
\x24$next = x24;
\x25$next = x25;
\x26$next = x26;
\x27$next = x27;
\x28$next = x28;
\x29$next = x29;
\x30$next = x30;
\x31$next = x31;
casez (\$494 )
/* src = "18_mandelbrot/cpu.py:289" */
1'h1:
(* full_case = 32'd1 *)
casez (instr[11:7])
5'h00:
\x0$next = \$538 [31:0];
5'h01:
\x1$next = \$561 [31:0];
5'h02:
\x2$next = \$584 [31:0];
5'h03:
\x3$next = \$607 [31:0];
5'h04:
\x4$next = \$630 [31:0];
5'h05:
\x5$next = \$653 [31:0];
5'h06:
\x6$next = \$676 [31:0];
5'h07:
\x7$next = \$699 [31:0];
5'h08:
\x8$next = \$722 [31:0];
5'h09:
\x9$next = \$745 [31:0];
5'h0a:
\x10$next = \$768 [31:0];
5'h0b:
\x11$next = \$791 [31:0];
5'h0c:
\x12$next = \$814 [31:0];
5'h0d:
\x13$next = \$837 [31:0];
5'h0e:
\x14$next = \$860 [31:0];
5'h0f:
\x15$next = \$883 [31:0];
5'h10:
\x16$next = \$906 [31:0];
5'h11:
\x17$next = \$929 [31:0];
5'h12:
\x18$next = \$952 [31:0];
5'h13:
\x19$next = \$975 [31:0];
5'h14:
\x20$next = \$998 [31:0];
5'h15:
\x21$next = \$1021 [31:0];
5'h16:
\x22$next = \$1044 [31:0];
5'h17:
\x23$next = \$1067 [31:0];
5'h18:
\x24$next = \$1090 [31:0];
5'h19:
\x25$next = \$1113 [31:0];
5'h1a:
\x26$next = \$1136 [31:0];
5'h1b:
\x27$next = \$1159 [31:0];
5'h1c:
\x28$next = \$1182 [31:0];
5'h1d:
\x29$next = \$1205 [31:0];
5'h1e:
\x30$next = \$1228 [31:0];
5'h??:
\x31$next = \$1251 [31:0];
endcase
endcase
casez (slow_rst)
1'h1:
begin
\x0$next = 32'd0;
\x1$next = 32'd0;
\x2$next = 32'd0;
\x3$next = 32'd0;
\x4$next = 32'd0;
\x5$next = 32'd0;
\x6$next = 32'd0;
\x7$next = 32'd0;
\x8$next = 32'd0;
\x9$next = 32'd0;
\x10$next = 32'd0;
\x11$next = 32'd0;
\x12$next = 32'd0;
\x13$next = 32'd0;
\x14$next = 32'd0;
\x15$next = 32'd0;
\x16$next = 32'd0;
\x17$next = 32'd0;
\x18$next = 32'd0;
\x19$next = 32'd0;
\x20$next = 32'd0;
\x21$next = 32'd0;
\x22$next = 32'd0;
\x23$next = 32'd0;
\x24$next = 32'd0;
\x25$next = 32'd0;
\x26$next = 32'd0;
\x27$next = 32'd0;
\x28$next = 32'd0;
\x29$next = 32'd0;
\x30$next = 32'd0;
\x31$next = 32'd0;
end
endcase
end
always @* begin
if (\$auto$verilog_backend.cc:2083:dump_module$1 ) begin end
\x10$1255$next = \x10$1255 ;
casez (\$1276 )
/* src = "18_mandelbrot/cpu.py:289" */
1'h1:
casez (\$1278 )
/* src = "18_mandelbrot/cpu.py:292" */
1'h1:
\x10$1255$next = \$1299 [31:0];
endcase
endcase
casez (slow_rst)
1'h1:
\x10$1255$next = 32'd0;
endcase
end
assign \$27 = \$32 ;
assign \$34 = \$35 ;
assign \$41 = \$48 ;
assign \$50 = \$57 ;
assign \$59 = \$66 ;
assign \$68 = \$75 ;
assign \$77 = \$84 ;
assign \$86 = \$93 ;
assign \$95 = \$102 ;
assign \$104 = \$111 ;
assign \$113 = \$120 ;
assign \$122 = \$129 ;
assign \$131 = \$138 ;
assign \$140 = \$147 ;
assign \$149 = \$156 ;
assign \$158 = \$165 ;
assign \$167 = \$174 ;
assign \$176 = \$183 ;
assign \$185 = \$192 ;
assign \$194 = \$201 ;
assign \$203 = \$210 ;
assign \$212 = \$219 ;
assign \$221 = \$228 ;
assign \$230 = \$237 ;
assign \$239 = \$246 ;
assign \$248 = \$255 ;
assign \$257 = \$264 ;
assign \$266 = \$273 ;
assign \$275 = \$282 ;
assign \$284 = \$291 ;
assign \$293 = \$300 ;
assign \$302 = \$309 ;
assign \$311 = \$318 ;
assign \$320 = \$327 ;
assign \$339 = \$346 ;
assign \$384 = \$397 ;
assign \$405 = \$408 ;
assign \$496 = \$515 ;
assign \$519 = \$538 ;
assign \$542 = \$561 ;
assign \$565 = \$584 ;
assign \$588 = \$607 ;
assign \$611 = \$630 ;
assign \$634 = \$653 ;
assign \$657 = \$676 ;
assign \$680 = \$699 ;
assign \$703 = \$722 ;
assign \$726 = \$745 ;
assign \$749 = \$768 ;
assign \$772 = \$791 ;
assign \$795 = \$814 ;
assign \$818 = \$837 ;
assign \$841 = \$860 ;
assign \$864 = \$883 ;
assign \$887 = \$906 ;
assign \$910 = \$929 ;
assign \$933 = \$952 ;
assign \$956 = \$975 ;
assign \$979 = \$998 ;
assign \$1002 = \$1021 ;
assign \$1025 = \$1044 ;
assign \$1048 = \$1067 ;
assign \$1071 = \$1090 ;
assign \$1094 = \$1113 ;
assign \$1117 = \$1136 ;
assign \$1140 = \$1159 ;
assign \$1163 = \$1182 ;
assign \$1186 = \$1205 ;
assign \$1209 = \$1228 ;
assign \$1232 = \$1251 ;
assign \$1280 = \$1299 ;
assign mem_wmask = \$472 ;
assign mem_rstrb = \$462 ;
assign mem_addr = \$450 ;
assign store_wmask = \$448 ;
assign mem_wdata[31:24] = \$434 ;
assign mem_wdata[23:16] = \$430 ;
assign mem_wdata[15:8] = \$428 ;
assign mem_wdata[7:0] = rs2[7:0];
assign loadData = \$426 ;
assign loadSign = \$422 ;
assign loadByte = \$416 ;
assign loadHalfword = \$414 ;
assign memHalfwordAccess = \$412 ;
assign memByteAccess = \$410 ;
assign loadStoreAddr = \$408 [31:0];
assign aluPlus = \$35 [31:0];
assign aluMinus = \$32 [32:0];
assign shamt = \$25 ;
assign aluIn2 = \$21 ;
assign aluIn1 = rs1;
assign Jimm = { instr[31], instr[31], instr[31], instr[31], instr[31], instr[31], instr[31], instr[31], instr[31], instr[31], instr[31], instr[31], instr[19:12], instr[20], instr[30:21], 1'h0 };
assign Bimm = { instr[31], instr[31], instr[31], instr[31], instr[31], instr[31], instr[31], instr[31], instr[31], instr[31], instr[31], instr[31], instr[31], instr[31], instr[31], instr[31], instr[31], instr[31], instr[31], instr[31], instr[7], instr[30:25], instr[11:8], 1'h0 };
assign Simm = { instr[31], instr[31], instr[31], instr[31], instr[31], instr[31], instr[31], instr[31], instr[31], instr[31], instr[31], instr[31], instr[31], instr[31], instr[31], instr[31], instr[31], instr[31], instr[31], instr[31], instr[31:25], instr[11:7] };
assign Iimm = { instr[31], instr[31], instr[31], instr[31], instr[31], instr[31], instr[31], instr[31], instr[31], instr[31], instr[31], instr[31], instr[31], instr[31], instr[31], instr[31], instr[31], instr[31], instr[31], instr[31], instr[31:20] };
assign Uimm = { instr[31:12], 12'h000 };
assign isSystem = \$19 ;
assign isStore = \$17 ;
assign isLoad = \$15 ;
assign isLUI = \$13 ;
assign isAUIPC = \$11 ;
assign isJAL = \$9 ;
assign isJALR = \$7 ;
assign isBranch = \$5 ;
assign isALUimm = \$3 ;
assign isALUreg = \$1 ;
endmodule
Raw
original_cpu.v
/* originally from https://github.com/BrunoLevy/learn-fpga/blob/master/FemtoRV/TUTORIALS/FROM_BLINKER_TO_RISCV/step18.v */
/**
* Step 18: Creating a RISC-V processor
* Mandelbrot in the terminal
*/
`default_nettype none
`include "clockworks.v"
`include "emitter_uart.v"
module Memory (
input clk,
input [31:0] mem_addr, // address to be read
output reg [31:0] mem_rdata, // data read from memory
input mem_rstrb, // goes high when processor wants to read
input [31:0] mem_wdata, // data to be written
input [3:0] mem_wmask // masks for writing the 4 bytes (1=write byte)
);
reg [31:0] MEM [0:1535]; // 1536 4-bytes words = 6 Kb of RAM in total
`ifdef BENCH
localparam slow_bit=12;
`else
localparam slow_bit=17;
`endif
// Memory-mapped IO in IO page, 1-hot addressing in word address.
localparam IO_LEDS_bit = 0; // W five leds
localparam IO_UART_DAT_bit = 1; // W data to send (8 bits)
localparam IO_UART_CNTL_bit = 2; // R status. bit 9: busy sending
// Converts an IO_xxx_bit constant into an offset in IO page.
function [31:0] IO_BIT_TO_OFFSET;
input [31:0] bitid;
begin
IO_BIT_TO_OFFSET = 1 << (bitid + 2);
end
endfunction
`include "riscv_assembly.v"
`define mandel_shift 10
`define mandel_mul (1 << `mandel_shift)
`define xmin (-2*`mandel_mul)
`define xmax ( 2*`mandel_mul)
`define ymin (-2*`mandel_mul)
`define ymax ( 2*`mandel_mul)
`define dx ((`xmax-`xmin)/80)
`define dy ((`ymax-`ymin)/80)
`define norm_max (4 << `mandel_shift)
integer mandelstart_ = 12;
integer blink_ = 16;
integer loop_y_ = 76;
integer loop_x_ = 84;
integer loop_Z_ = 96;
integer exit_Z_ = 188;
integer wait_ = 264;
integer wait_L0_ = 272;
integer putc_ = 284;
integer putc_L0_ = 292;
integer mulsi3_ = 308;
integer mulsi3_L0_ = 316;
integer mulsi3_L1_ = 328;
integer colormap_ = 344;
// X,Y : s0,s1
// Cr,Ci : s2,s3
// Zr,Zi : s4,s5
// Zrr,2Zri,Zii: s6,s7,s8
// cnt: s10
// 128: s11
initial begin
LI(sp,32'h1800); // End of RAM, 6kB
LI(gp,32'h400000); // IO page
Label(mandelstart_);
// Blink 5 times.
LI(s0,5);
Label(blink_);
LI(a0,5);
SW(a0,gp,IO_BIT_TO_OFFSET(IO_LEDS_bit));
CALL(LabelRef(wait_));
LI(a0,10);
SW(a0,gp,IO_BIT_TO_OFFSET(IO_LEDS_bit));
CALL(LabelRef(wait_));
ADDI(s0,s0,-1);
BNEZ(s0,LabelRef(blink_));
LI(a0,0);
SW(a0,gp,IO_BIT_TO_OFFSET(IO_LEDS_bit));
LI(s1,0);
LI(s3,`xmin);
LI(s11,80);
Label(loop_y_);
LI(s0,0);
LI(s2,`ymin);
Label(loop_x_);
MV(s4,s2); // Z <- C
MV(s5,s3);
LI(s10,9); // iter <- 9
Label(loop_Z_);
MV(a0,s4); // Zrr <- (Zr*Zr) >> mandel_shift
MV(a1,s4);
CALL(LabelRef(mulsi3_));
SRLI(s6,a0,`mandel_shift);
MV(a0,s4); // Zri <- (Zr*Zi) >> (mandel_shift-1)
MV(a1,s5);
CALL(LabelRef(mulsi3_));
SRAI(s7,a0,`mandel_shift-1);
MV(a0,s5); // Zii <- (Zi*Zi) >> (mandel_shift)
MV(a1,s5);
CALL(LabelRef(mulsi3_));
SRLI(s8,a0,`mandel_shift);
SUB(s4,s6,s8); // Zr <- Zrr - Zii + Cr
ADD(s4,s4,s2);
ADD(s5,s7,s3); // Zi <- 2Zri + Cr
ADD(s6,s6,s8); // if norm > norm max, exit loop
LI(s7,`norm_max);
BGT(s6,s7,LabelRef(exit_Z_));
ADDI(s10,s10,-1); // iter--, loop if non-zero
BNEZ(s10,LabelRef(loop_Z_));
Label(exit_Z_);
LI(a0,colormap_);
ADD(a0,a0,s10);
LBU(a0,a0,0);
CALL(LabelRef(putc_));
ADDI(s0,s0,1);
ADDI(s2,s2,`dx);
BNE(s0,s11,LabelRef(loop_x_));
LI(a0," ");
CALL(LabelRef(putc_));
LI(a0,"\n");
CALL(LabelRef(putc_));
ADDI(s1,s1,1);
ADDI(s3,s3,`dy);
BNE(s1,s11,LabelRef(loop_y_));
J(LabelRef(mandelstart_));
EBREAK(); // I systematically keep it before functions
// in case I decide to remove the loop...
Label(wait_);
LI(t0,1);
SLLI(t0,t0,slow_bit);
Label(wait_L0_);
ADDI(t0,t0,-1);
BNEZ(t0,LabelRef(wait_L0_));
RET();
Label(putc_);
// Send character to UART
SW(a0,gp,IO_BIT_TO_OFFSET(IO_UART_DAT_bit));
// Read UART status, and loop until bit 9 (busy sending)
// is zero.
LI(t0,1<<9);
Label(putc_L0_);
LW(t1,gp,IO_BIT_TO_OFFSET(IO_UART_CNTL_bit));
AND(t1,t1,t0);
BNEZ(t1,LabelRef(putc_L0_));
RET();
// Mutiplication routine,
// Input in a0 and a1
// Result in a0
Label(mulsi3_);
MV(a2,a0);
LI(a0,0);
Label(mulsi3_L0_);
ANDI(a3,a1,1);
BEQZ(a3,LabelRef(mulsi3_L1_));
ADD(a0,a0,a2);
Label(mulsi3_L1_);
SRLI(a1,a1,1);
SLLI(a2,a2,1);
BNEZ(a1,LabelRef(mulsi3_L0_));
RET();
Label(colormap_);
DATAB(" ",".",",",":");
DATAB(";","o","x","%");
DATAB("#","@", 0 , 0 );
endASM();
end
wire [29:0] word_addr = mem_addr[31:2];
always @(posedge clk) begin
if(mem_rstrb) begin
mem_rdata <= MEM[word_addr];
end
if(mem_wmask[0]) MEM[word_addr][ 7:0 ] <= mem_wdata[ 7:0 ];
if(mem_wmask[1]) MEM[word_addr][15:8 ] <= mem_wdata[15:8 ];
if(mem_wmask[2]) MEM[word_addr][23:16] <= mem_wdata[23:16];
if(mem_wmask[3]) MEM[word_addr][31:24] <= mem_wdata[31:24];
end
endmodule
module Processor (
input clk,
input resetn,
output [31:0] mem_addr,
input [31:0] mem_rdata,
output mem_rstrb,
output [31:0] mem_wdata,
output [3:0] mem_wmask
);
reg [31:0] PC=0; // program counter
reg [31:0] instr; // current instruction
// See the table P. 105 in RISC-V manual
// The 10 RISC-V instructions
wire isALUreg = (instr[6:0] == 7'b0110011); // rd <- rs1 OP rs2
wire isALUimm = (instr[6:0] == 7'b0010011); // rd <- rs1 OP Iimm
wire isBranch = (instr[6:0] == 7'b1100011); // if(rs1 OP rs2) PC<-PC+Bimm
wire isJALR = (instr[6:0] == 7'b1100111); // rd <- PC+4; PC<-rs1+Iimm
wire isJAL = (instr[6:0] == 7'b1101111); // rd <- PC+4; PC<-PC+Jimm
wire isAUIPC = (instr[6:0] == 7'b0010111); // rd <- PC + Uimm
wire isLUI = (instr[6:0] == 7'b0110111); // rd <- Uimm
wire isLoad = (instr[6:0] == 7'b0000011); // rd <- mem[rs1+Iimm]
wire isStore = (instr[6:0] == 7'b0100011); // mem[rs1+Simm] <- rs2
wire isSYSTEM = (instr[6:0] == 7'b1110011); // special
// The 5 immediate formats
wire [31:0] Uimm={ instr[31], instr[30:12], {12{1'b0}}};
wire [31:0] Iimm={{21{instr[31]}}, instr[30:20]};
wire [31:0] Simm={{21{instr[31]}}, instr[30:25],instr[11:7]};
wire [31:0] Bimm={{20{instr[31]}}, instr[7],instr[30:25],instr[11:8],1'b0};
wire [31:0] Jimm={{12{instr[31]}}, instr[19:12],instr[20],instr[30:21],1'b0};
// Source and destination registers
wire [4:0] rs1Id = instr[19:15];
wire [4:0] rs2Id = instr[24:20];
wire [4:0] rdId = instr[11:7];
// function codes
wire [2:0] funct3 = instr[14:12];
wire [6:0] funct7 = instr[31:25];
// The registers bank
reg [31:0] RegisterBank [0:31];
reg [31:0] rs1; // value of source
reg [31:0] rs2; // registers.
wire [31:0] writeBackData; // data to be written to rd
wire writeBackEn; // asserted if data should be written to rd
`ifdef BENCH
integer i;
initial begin
for(i=0; i<32; ++i) begin
RegisterBank[i] = 0;
end
end
`endif
// The ALU
wire [31:0] aluIn1 = rs1;
wire [31:0] aluIn2 = isALUreg | isBranch ? rs2 : Iimm;
wire [4:0] shamt = isALUreg ? rs2[4:0] : instr[24:20]; // shift amount
// The adder is used by both arithmetic instructions and JALR.
wire [31:0] aluPlus = aluIn1 + aluIn2;
// Use a single 33 bits subtract to do subtraction and all comparisons
// (trick borrowed from swapforth/J1)
wire [32:0] aluMinus = {1'b1, ~aluIn2} + {1'b0,aluIn1} + 33'b1;
wire LT = (aluIn1[31] ^ aluIn2[31]) ? aluIn1[31] : aluMinus[32];
wire LTU = aluMinus[32];
wire EQ = (aluMinus[31:0] == 0);
// Flip a 32 bit word. Used by the shifter (a single shifter for
// left and right shifts, saves silicium !)
function [31:0] flip32;
input [31:0] x;
flip32 = {x[ 0], x[ 1], x[ 2], x[ 3], x[ 4], x[ 5], x[ 6], x[ 7],
x[ 8], x[ 9], x[10], x[11], x[12], x[13], x[14], x[15],
x[16], x[17], x[18], x[19], x[20], x[21], x[22], x[23],
x[24], x[25], x[26], x[27], x[28], x[29], x[30], x[31]};
endfunction
wire [31:0] shifter_in = (funct3 == 3'b001) ? flip32(aluIn1) : aluIn1;
/* verilator lint_off WIDTH */
wire [31:0] shifter =
$signed({instr[30] & aluIn1[31], shifter_in}) >>> aluIn2[4:0];
/* verilator lint_on WIDTH */
wire [31:0] leftshift = flip32(shifter);
// ADD/SUB/ADDI:
// funct7[5] is 1 for SUB and 0 for ADD. We need also to test instr[5]
// to make the difference with ADDI
//
// SRLI/SRAI/SRL/SRA:
// funct7[5] is 1 for arithmetic shift (SRA/SRAI) and
// 0 for logical shift (SRL/SRLI)
reg [31:0] aluOut;
always @(*) begin
case(funct3)
3'b000: aluOut = (funct7[5] & instr[5]) ? aluMinus[31:0] : aluPlus;
3'b001: aluOut = leftshift;
3'b010: aluOut = {31'b0, LT};
3'b011: aluOut = {31'b0, LTU};
3'b100: aluOut = (aluIn1 ^ aluIn2);
3'b101: aluOut = shifter;
3'b110: aluOut = (aluIn1 | aluIn2);
3'b111: aluOut = (aluIn1 & aluIn2);
endcase
end
// The predicate for branch instructions
reg takeBranch;
always @(*) begin
case(funct3)
3'b000: takeBranch = EQ;
3'b001: takeBranch = !EQ;
3'b100: takeBranch = LT;
3'b101: takeBranch = !LT;
3'b110: takeBranch = LTU;
3'b111: takeBranch = !LTU;
default: takeBranch = 1'b0;
endcase
end
// Address computation
// An adder used to compute branch address, JAL address and AUIPC.
// branch->PC+Bimm AUIPC->PC+Uimm JAL->PC+Jimm
// Equivalent to PCplusImm = PC + (isJAL ? Jimm : isAUIPC ? Uimm : Bimm)
wire [31:0] PCplusImm = PC + ( instr[3] ? Jimm[31:0] :
instr[4] ? Uimm[31:0] :
Bimm[31:0] );
wire [31:0] PCplus4 = PC+4;
// register write back
assign writeBackData = (isJAL || isJALR) ? PCplus4 :
isLUI ? Uimm :
isAUIPC ? PCplusImm :
isLoad ? LOAD_data :
aluOut;
wire [31:0] nextPC = ((isBranch && takeBranch) || isJAL) ? PCplusImm :
isJALR ? {aluPlus[31:1],1'b0} :
PCplus4;
wire [31:0] loadstore_addr = rs1 + (isStore ? Simm : Iimm);
// Load
// All memory accesses are aligned on 32 bits boundary. For this
// reason, we need some circuitry that does unaligned halfword
// and byte load/store, based on:
// - funct3[1:0]: 00->byte 01->halfword 10->word
// - mem_addr[1:0]: indicates which byte/halfword is accessed
wire mem_byteAccess = funct3[1:0] == 2'b00;
wire mem_halfwordAccess = funct3[1:0] == 2'b01;
wire [15:0] LOAD_halfword =
loadstore_addr[1] ? mem_rdata[31:16] : mem_rdata[15:0];
wire [7:0] LOAD_byte =
loadstore_addr[0] ? LOAD_halfword[15:8] : LOAD_halfword[7:0];
// LOAD, in addition to funct3[1:0], LOAD depends on:
// - funct3[2] (instr[14]): 0->do sign expansion 1->no sign expansion
wire LOAD_sign =
!funct3[2] & (mem_byteAccess ? LOAD_byte[7] : LOAD_halfword[15]);
wire [31:0] LOAD_data =
mem_byteAccess ? {{24{LOAD_sign}}, LOAD_byte} :
mem_halfwordAccess ? {{16{LOAD_sign}}, LOAD_halfword} :
mem_rdata ;
// Store
// ------------------------------------------------------------------------
assign mem_wdata[ 7: 0] = rs2[7:0];
assign mem_wdata[15: 8] = loadstore_addr[0] ? rs2[7:0] : rs2[15: 8];
assign mem_wdata[23:16] = loadstore_addr[1] ? rs2[7:0] : rs2[23:16];
assign mem_wdata[31:24] = loadstore_addr[0] ? rs2[7:0] :
loadstore_addr[1] ? rs2[15:8] : rs2[31:24];
// The memory write mask:
// 1111 if writing a word
// 0011 or 1100 if writing a halfword
// (depending on loadstore_addr[1])
// 0001, 0010, 0100 or 1000 if writing a byte
// (depending on loadstore_addr[1:0])
wire [3:0] STORE_wmask =
mem_byteAccess ?
(loadstore_addr[1] ?
(loadstore_addr[0] ? 4'b1000 : 4'b0100) :
(loadstore_addr[0] ? 4'b0010 : 4'b0001)
) :
mem_halfwordAccess ?
(loadstore_addr[1] ? 4'b1100 : 4'b0011) :
4'b1111;
// The state machine
localparam FETCH_INSTR = 0;
localparam WAIT_INSTR = 1;
localparam FETCH_REGS = 2;
localparam EXECUTE = 3;
localparam LOAD = 4;
localparam WAIT_DATA = 5;
localparam STORE = 6;
reg [2:0] state = FETCH_INSTR;
always @(posedge clk) begin
if(!resetn) begin
PC <= 0;
state <= FETCH_INSTR;
end else begin
if(writeBackEn && rdId != 0) begin
RegisterBank[rdId] <= writeBackData;
// $display("r%0d <= %b (%d) (%d)",rdId,writeBackData,writeBackData,$signed(writeBackData));
// For displaying what happens.
end
case(state)
FETCH_INSTR: begin
state <= WAIT_INSTR;
end
WAIT_INSTR: begin
instr <= mem_rdata;
state <= FETCH_REGS;
end
FETCH_REGS: begin
rs1 <= RegisterBank[rs1Id];
rs2 <= RegisterBank[rs2Id];
state <= EXECUTE;
end
EXECUTE: begin
if(!isSYSTEM) begin
PC <= nextPC;
end
state <= isLoad ? LOAD :
isStore ? STORE :
FETCH_INSTR;
`ifdef BENCH
if(isSYSTEM) $finish();
`endif
end
LOAD: begin
state <= WAIT_DATA;
end
WAIT_DATA: begin
state <= FETCH_INSTR;
end
STORE: begin
state <= FETCH_INSTR;
end
endcase
end
end
assign writeBackEn = (state==EXECUTE && !isBranch && !isStore) ||
(state==WAIT_DATA) ;
assign mem_addr = (state == WAIT_INSTR || state == FETCH_INSTR) ?
PC : loadstore_addr ;
assign mem_rstrb = (state == FETCH_INSTR || state == LOAD);
assign mem_wmask = {4{(state == STORE)}} & STORE_wmask;
endmodule
module SOC (
input CLK, // system clock
input RESET, // reset button
output reg [4:0] LEDS, // system LEDs
input RXD, // UART receive
output TXD // UART transmit
);
wire clk;
wire resetn;
wire [31:0] mem_addr;
wire [31:0] mem_rdata;
wire mem_rstrb;
wire [31:0] mem_wdata;
wire [3:0] mem_wmask;
Processor CPU(
.clk(clk),
.resetn(resetn),
.mem_addr(mem_addr),
.mem_rdata(mem_rdata),
.mem_rstrb(mem_rstrb),
.mem_wdata(mem_wdata),
.mem_wmask(mem_wmask)
);
wire [31:0] RAM_rdata;
wire [29:0] mem_wordaddr = mem_addr[31:2];
wire isIO = mem_addr[22];
wire isRAM = !isIO;
wire mem_wstrb = |mem_wmask;
Memory RAM(
.clk(clk),
.mem_addr(mem_addr),
.mem_rdata(RAM_rdata),
.mem_rstrb(isRAM & mem_rstrb),
.mem_wdata(mem_wdata),
.mem_wmask({4{isRAM}}&mem_wmask)
);
// Memory-mapped IO in IO page, 1-hot addressing in word address.
localparam IO_LEDS_bit = 0; // W five leds
localparam IO_UART_DAT_bit = 1; // W data to send (8 bits)
localparam IO_UART_CNTL_bit = 2; // R status. bit 9: busy sending
always @(posedge clk) begin
if(isIO & mem_wstrb & mem_wordaddr[IO_LEDS_bit]) begin
LEDS <= mem_wdata;
// $display("Value sent to LEDS: %b %d %d",mem_wdata,mem_wdata,$signed(mem_wdata));
end
end
wire uart_valid = isIO & mem_wstrb & mem_wordaddr[IO_UART_DAT_bit];
wire uart_ready;
corescore_emitter_uart #(
.clk_freq_hz(`CPU_FREQ*1000000),
.baud_rate(1000000)
) UART(
.i_clk(clk),
.i_rst(!resetn),
.i_data(mem_wdata[7:0]),
.i_valid(uart_valid),
.o_ready(uart_ready),
.o_uart_tx(TXD)
);
wire [31:0] IO_rdata =
mem_wordaddr[IO_UART_CNTL_bit] ? { 22'b0, !uart_ready, 9'b0}
: 32'b0;
assign mem_rdata = isRAM ? RAM_rdata :
IO_rdata ;
`ifdef BENCH
always @(posedge clk) begin
if(uart_valid) begin
$write("%c", mem_wdata[7:0] );
$fflush(32'h8000_0001);
end
end
`endif
// Gearbox and reset circuitry.
Clockworks CW(
.CLK(CLK),
.RESET(RESET),
.clk(clk),
.resetn(resetn)
);
endmodule
@bl0x
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bl0x commented Feb 28, 2023

The original has the full SOC including the Mandelbrot assembly code.

Verilog output from Amaranth is kind of readable, but definitely more verbose than the original.

@suarezvictor
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Author

You're right, I just wanted to show just the CPU but copied more than I intended
If the code is barely readable is ok to me, this is just to understand what's going on
It's good to know that the Amaranth implementation is shorter, and in my view, cleaner

@bl0x
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bl0x commented Feb 28, 2023

There's also quite some low hanging fruit to make it even cleaner. That'll have to wait a bit though

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