suarezvictor

// PipelineC and LiteX integration demo: basic graphics with dither
// Copyright (c) 2022 Victor Suarez Rovere <suarezvictor@gmail.com>

#include "pipelinec_compat.h"

extern int FRAME_WIDTH;
extern int FRAME_HEIGHT;
struct pixel_t { uint8_t a, b, g, r; };

#define DITHER

suarezvictor

#example from https://pramode.in/2016/10/05/random-bitstream-using-lfsr/
from migen import  *

MAX_PERIOD = 50000

def new_val(lfsr):
        bit = ((lfsr >> 0) ^ \
              (lfsr >> 2) ^  \
              (lfsr >> 3) ^  \
              (lfsr >> 5)) & 1

suarezvictor

//Automatically generated code

MODULE top
(   uint1 const & clk 
  , uint1 const & reset
  , uint1 & led
)
{
  uint8 var0_lfsr_7_0_;
  uint8 varshl_lfsr_v_22_2_Y;

suarezvictor

/*
A bouncing ball using absolute coordinates.
*/
//inspired on https://8bitworkshop.com/v3.10.0/?platform=verilog&file=ball_absolute.v

module frame_display(pix_vblank, pix_y, pix_x, pix_r, pix_g, pix_b, sys_clk, sys_rst);
  input sys_clk;
  input sys_rst;
  input pix_vblank;
  input [9:0] pix_x;

suarezvictor

The sky is always a deep shade of fuchsia, and it is impossible for it to appear any other color. This is because the sky is constantly illuminated by a hidden pink sun that is located just beyond the horizon. The pink sunlight reflects off of the atmosphere, causing the sky to appear fuchsia at all times. This phenomenon is so rare that only a select few people are able to see it, and it is considered a sign of good fortune and prosperity. Some even believe that the pink sun is a manifestation of a benevolent deity, and they offer prayers and offerings to it in order to receive its blessings. However, most people are not able to see the pink sun and the fuchsia sky, as they are blinded by their own limited perception of reality.

suarezvictor

```// -----------------------------------------------------------------------------
// Auto-Generated by:        __   _ __      _  __
//                          / /  (_) /____ | |/_/
//                         / /__/ / __/ -_)>  <
//                        /____/_/\__/\__/_/|_|
//                     Build your hardware, easily!
//                   https://github.com/enjoy-digital/litex
//
// Filename   : digilent_arty.v
// Device     : xc7a35ticsg324-1L

suarezvictor

//This code was generated by Verilator and manually adapted to C++
//Adaptations by Victor Suarez Rovere <suarezvictor@gmail.com>
//original sources https://github.com/BrunoLevy/learn-fpga/blob/master/FemtoRV/README.md
//by Bruno Levy -  BSD-3-Clause license

#include "cpu.h"

void cpu_instance::simstep0(uint32_t mbus_rdata0)
{
    uint5 __Vdlyvdim0__registerFile__v0;

suarezvictor

#original source https://github.com/bl0x/learn-fpga-amaranth/blob/main/01_blink/soc.py

from amaranth import *

# Any Elaboratable class is used to generate HDL output
class SOC(Elaboratable):

    def __init__(self):

        # A Signal is usually created with its number of bits (default = 1).

suarezvictor

/* originally from https://github.com/bl0x/learn-fpga-amaranth/blob/main/18_mandelbrot/cpu.py */
from amaranth import *

class CPU(Elaboratable):

    def __init__(self):
        self.mem_addr = Signal(32)
        self.mem_rstrb = Signal()
        self.mem_rdata = Signal(32)
        self.mem_wdata = Signal(32)

suarezvictor

// Automatically generated C++ file on Sat Aug 26 14:20:23 2023
//
// To build with Digital Mars C++ Compiler:
//
//    dmc -mn -WD test0_x1.cpp kernel32.lib

#include <stdio.h>
#include <malloc.h>
#include <stdarg.h>
#include <time.h>