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@swharden
Created February 5, 2023 15:06
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// C code from the AD7705/AD7706 datasheet
// https://www.analog.com/media/en/technical-documentation/data-sheets/ad7705_7706.pdf
#include <math.h>
#include <io6811.h>
#define NUM_SAMPLES 1000 /* change the number of data samples */
#define MAX_REG_LENGTH 2 /* this says that the max length of a register is 2 bytes */
Writetoreg(int);
Read(int, char);
char *datapointer = store;
char store[NUM_SAMPLES * MAX_REG_LENGTH + 30];
void main()
{
/* the only pin that is programmed here from the 68HC11 is the /CS
* and this is why the PC2 bit of PORTC is made as an output */
char a;
DDRC = 0x04; /* PC2 is an output the rest of the port bits are inputs */
PORTC | = 0x04; /* make the /CS line high */
Writetoreg(0x20); /* Active Channel is Ain1(+)/Ain1(−), next operation as write to the clock register */
Writetoreg(0x0C); /* master clock enabled, 4.9512MHz Clock, set output rate to 50Hz*/
Writetoreg(0x10); /* Active Channel is Ain1(+)/Ain1(−), next operation as write to the setup register */
Writetoreg(0x40); /* gain = 1, bipolar mode, buffer off, clear FSYNC and perform a Self Calibration*/
while (PORTC & 0x10); /* wait for /DRDY to go low */
for (a = 0; a < NUM_SAMPLES; a++)
{
Writetoreg(0x38); /*set the next operation for 16 bit read from the data register */
Read(NUM_SAMPES, 2);
}
}
Writetoreg(int byteword);
{
int q;
SPCR = 0x3f;
/* WiredOR mode(DWOM=1),
Master mode(MSTR=1),
SCK idles high(CPOL=1),
/SS can be low always (CPHA=1),
lowest clock speed(slowest speed which is master clock /32
*/
SPCR = 0X7f;
DDRD = 0x18; /* SCK, MOSI outputs */
q = SPSR;
/* the read of the status register and of the data register is needed to clear
the interrupt which tells the user that the data transfer is complete */
q = SPDR;
PORTC &= 0xfb; /* /CS is low */
SPDR = byteword; /* put the byte into data register */
while (!(SPSR & 0x80)); /* wait for /DRDY to go low */
PORTC |= 0x4; /* /CS high */
}
Read(int amount, int reglength)
{
int q;
SPCR = 0x3f;
SPCR = 0x7f; /* clear the interrupt */
DDRD = 0x10; /* MOSI output, MISO input, SCK output */
while (PORTC & 0x10); /* wait for /DRDY to go low */
PORTC & 0xfb; /* /CS is low */
for (b = 0; b < reglength; b++)
{
SPDR = 0;
while (!(SPSR & 0x80))
; /* wait until port ready before reading */
*datapointer++ = SPDR; /* read SPDR into store array via datapointer */
}
PORTC |= 4; /* /CS is high */
}
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