swh swhsiang

## my_ftx_link.txt
https://ftx.com/#a=15376828

## dummy.vhdl
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_UNSIGNED.all;

entity step3 is
    port(CLK, reset, switch: in std_logic;
            Q: out std_logic_vector(0 to 6));
end step3;

architecture behavioral of step3 is
	library ieee;
	use ieee.std_logic_1164.all;
	use ieee.std_logic_UNSIGNED.all;

	entity step3 is
	port(CLK, reset, switch: in std_logic;
	Q: out std_logic_vector(0 to 6));
	end step3;

	architecture behavioral of step3 is