dummy.vhdl

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_UNSIGNED.all;

entity step3 is                         
    port(CLK, reset, switch: in std_logic;
            Q: out std_logic_vector(0 to 6));
end step3;

architecture behavioral of step3 is
begin  

process(CLK, reset, switch)
variable counter: std_logic_vector (3 downto 0);
variable init, mode: std_logic := ‘0’;
    begin
    if   (reset='0' or switch /= mode) then
	init := ‘0’
    elsif  CLK'event and CLK='1' then
	if init = ‘0’ then
		mode := switch;
		init := ‘1’;
		-- even
		if mode = ‘0’ then
			counter := “0000”;
		else
			counter := “0001”;
		end if;
	end if;
           counter := counter + 2;
    end if;

CASE (counter) IS
    WHEN "0000"  => out  <=  "0000001" ;
    WHEN "0001"  => out  <=  "1001111" ;
    WHEN "0010"  => out  <=  "0010010" ;
    WHEN "0011"  => out  <=  "0000110" ;
    WHEN "0100"  => out  <=  "1001100" ;
    WHEN "0101"  => out  <=  "0100100" ;
    WHEN "0110"  => out  <=  "0100000" ;
    WHEN "0111"  => out  <=  "0001111" ;
    WHEN "1000"  => out  <= "0000000" ;
    WHEN "1001"  => out  <= "0001100" ;
    when others  => out  <=  "1111111";
    END CASE ;

    end process;
end behavioral;