ff.sv

module ff #(
  bit ASYNC_RESET = 1,
  bit ACTIVE_LOW  = 1
)(
  input   var i_clk,
  input   var i_rst_n,
  input   var i_rst,
  input   var i_d,
  output  var o_d
);
  logic async_rst_n;
  logic async_rst;
  logic rst_n;
  logic rst;

  if (!ASYNC_RESET) begin
    assign  async_rst_n = '1;
    assign  async_rst   = '0;
  end
  else if (ACTIVE_LOW) begin
    assign  async_rst_n = i_rst_n;
    assign  async_rst   = '0;
  end
  else begin
    assign  async_rst_n = '1;
    assign  async_rst   = i_rst;
  end

  if (ACTIVE_LOW) begin
    assign  rst_n = i_rst_n;
    assign  rst   = '0;
  end
  else begin
    assign  rst_n = '1;
    assign  rst   = i_rst;
  end

  always_ff @(posedge i_clk, negedge async_rst_n, posedge async_rst) begin
    if ((!rst_n) || rst)  o_d <= '0;
    else                  o_d <= i_d;
  end
endmodule