taichi-ishitani

#! /bin/bash

dvhcom sub.vhd
dvlcom top.sv
dsim -genimage image -top work.top

taichi-ishitani

require 'yaml'
require 'delegate'

module MyNodeExtension
  refine Psych::Nodes::Node do
    def mapping_key?
      @mapping_key
    end

    attr_writer :mapping_key

taichi-ishitani

{
  // IntelliSense を使用して利用可能な属性を学べます。
  // 既存の属性の説明をホバーして表示します。
  // 詳細情報は次を確認してください: https://go.microsoft.com/fwlink/?linkid=830387
  "version": "0.2.0",
  "configurations": [
    {
      "type": "rdbg",
      "name": "Debug current spec file with rdbg",
      "request": "launch",

taichi-ishitani

interface qiita_bus_if
  import  qiita_bus_pkg::*;
#(
  parameter qiita_bus_config  BUS_CONFIG  = '0
);
  logic                                 scmd_accept;
  qiita_bus_command                     mcmd;
  logic [BUS_CONFIG.id_width-1:0]       mid;
  logic [BUS_CONFIG.address_width-1:0]  maddr;
  logic [BUS_CONFIG.data_width-1:0]     mdata;

taichi-ishitani

interface clock_gen;
  timeunit  1ns/1ps;

  bit clk;

  event     start_clock_event;
  realtime  high_period_ns;
  realtime  low_period_ns;

  function automatic void start_clock(

taichi-ishitani

display=`hostname`.mshome.net:0

if [ -f ~/.Xauthority ]; then
  if [ -z "$(xauth list | grep $display)" ]; then
    rm ~/.Xauthority
  fi
fi

if [ ! -f ~/.Xauthority ]; then
  xauth add $display MIT-MAGIC-COOKIE-1 $(openssl rand -hex 16) 2> /dev/null

taichi-ishitani

[[register_blocks]]
name      = 'block_0'
byte_size = 128
comment   = '''
this is block_1.
this block includes six registers.
'''

[[register_blocks.register_files]]
name            = 'register_file_0'

taichi-ishitani

# Before RgGen 0.17
- { name: foo_0, bit_assignment: { lsb: 0, width: 2 }, type: rw, initial_value: 0 }
- { name: foo_1, bit_assignment: { lsb: 2, width: 2 }, type: rw, initial_value: 1 }
- { name: foo_2, bit_assignment: { lsb: 4, width: 2 }, type: rw, initial_value: 2 }
- { name: foo_3, bit_assignment: { lsb: 6, width: 2 }, type: rw, initial_value: 3 }

---

# After RgGen 0.17
- <<:

taichi-ishitani

module ff #(
  bit ASYNC_RESET = 1,
  bit ACTIVE_LOW  = 1
)(
  input   var i_clk,
  input   var i_rst_n,
  input   var i_rst,
  input   var i_d,
  output  var o_d
);

taichi-ishitani

interface foo_if;
  logic [1:0] a;
  logic [1:0] b;
  logic [1:0] c;
endinterface

module top(
  input   var       i_clk,
  input   var       i_rst_n,
  input   var [1:0] i_a,