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taichi-ishitani/rggen_0p17.yml

Created November 14, 2019 14:45
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rggen_0p17.yml
# Before RgGen 0.17
- { name: foo_0, bit_assignment: { lsb: 0, width: 2 }, type: rw, initial_value: 0 }
- { name: foo_1, bit_assignment: { lsb: 2, width: 2 }, type: rw, initial_value: 1 }
- { name: foo_2, bit_assignment: { lsb: 4, width: 2 }, type: rw, initial_value: 2 }
- { name: foo_3, bit_assignment: { lsb: 6, width: 2 }, type: rw, initial_value: 3 }
---
# After RgGen 0.17
- <<:
- { name: foo, bit_assignment: { lsb: 0, width: 2, sequence_size: 4 }, type: rw }
- initial_value: [0, 1, 2, 3]
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