tonosaman/Howto-build-openocd.md

## Howto-build-openocd.md

      
    Raw
  

              Howto-build-openocd.md
            
          
    for RPi2 JTAG debugging with Olimex ARM-USB-OCD-H

System constitution


probe device: Olimex ARM-USB-OCD-H
target device: Raspberry Pi 2

files for booting: bootcode.bin, start.elf, config.txt from here
jtag target image armjtag.bin: from here
config.txt: edit to add a line kernel=armjtag.bin


host machine: Ubuntu 15.04

openocd-0.9.0 as debugger host:

probe device driver: libftd2xx1.1.12
probe device configuration: olimex-arm-usb-ocd-h.cfg (@see below)
target device configuration: openocd-rpi2.cfg (@see below)


debug client: telnet or gdb


pin assign between Olimex ARM-USB-OCD-H and Raspberry Pi 2

Setup FTDI proprietary D2XX driver

This method is obsolete. By openocd warning message, you should use libftdi.
locate libftd2xx.a libftd2xx.so.1.1.12


download FTDI proprietary D2XX driver for linux from here
installation guide is here
extract to ./libftd2xx1.1.12/
(optional) locate libraries to /usr/local/lib/

sudo cp libftd2xx1.1.12/build/x86_64/libftd2xx.a /usr/local/lib/
sudo cp libftd2xx1.1.12/build/x86_64/libtd2xx.so.1.1.12 /usr/local/lib/
sudo ln -s /usr/local/lib/libtd2xx.so.1.1.12 /usr/local/lib/libftd2xx.so
sudo chmod 0755 /usr/local/lib/libtd2xx.so.1.1.12
Build OpenOCD

Download "openocd-0.9.0 release" from here

extract to ./openocd-0.9.0

configure options

$ cd openocd-0.9.0
$ ./configure --enable-maintainer-mode --enable-legacy-ft2232_ftd2xx --with-ftd2xx-lib=static --with-ftd2xx-linux-tardir=../libftd2xx1.1.12
Add ld linkage to libpthread

--- src/Makefile.org	2015-07-16 17:51:11.333497970 +0900
+++ src/Makefile	2015-07-16 17:52:06.797236301 +0900
@@ -275,11 +275,11 @@
 INSTALL_SCRIPT = ${INSTALL}
 INSTALL_STRIP_PROGRAM = $(install_sh) -c -s
 LD = /usr/bin/ld -m elf_x86_64
-LDFLAGS =  -L/home/tono/OpenOCD/libftd2xx1.1.12/build/x86_64
+LDFLAGS =  -L/home/tono/OpenOCD/libftd2xx1.1.12/build/x86_64 -L/lib64
 LIBFTDI_CFLAGS = 
 LIBFTDI_LIBS = 
 LIBOBJS = 
-LIBS = -lftd2xx -lrt -ldl 
+LIBS = -lftd2xx -lrt -ldl -lpthread
 LIBTOOL = $(SHELL) $(top_builddir)/libtool
 LIBTOOL_DEPS = ./ltmain.sh
 LIBUSB0_CFLAGS = 
make

$ ldd openocd-0.9.0/src/openocd
	linux-vdso.so.1 =>  (0x00007ffc599bc000)
	libusb-0.1.so.4 => /lib/x86_64-linux-gnu/libusb-0.1.so.4 (0x00007f5dace03000)
	libusb-1.0.so.0 => /lib/x86_64-linux-gnu/libusb-1.0.so.0 (0x00007f5dacbeb000)
	libm.so.6 => /lib/x86_64-linux-gnu/libm.so.6 (0x00007f5dac8e3000)
	libdl.so.2 => /lib/x86_64-linux-gnu/libdl.so.2 (0x00007f5dac6df000)
	libpthread.so.0 => /lib/x86_64-linux-gnu/libpthread.so.0 (0x00007f5dac4c1000)
	libc.so.6 => /lib/x86_64-linux-gnu/libc.so.6 (0x00007f5dac0f7000)
	libudev.so.1 => /lib/x86_64-linux-gnu/libudev.so.1 (0x00007f5dabee4000)
	/lib64/ld-linux-x86-64.so.2 (0x00007f5dad00c000)

Paste to olimex-arm-usb-ocd-h.cfg : Configuretion file for openocd 1 of 2

# Olimex ARM-USB-OCD-H
# http://www.olimex.com/dev/arm-usb-ocd-h.html
interface ft2232
ft2232_device_desc "Olimex OpenOCD JTAG ARM-USB-OCD-H"
ft2232_layout olimex-jtag
ft2232_vid_pid 0x15ba 0x002b
Paste to openocd-rpi2.cfg : Configuretion file for openocd 2 of 2

from here
Thanks jitomesky! I bought your book!
# ref: http://www.raspberrypi.org/forums/viewtopic.php?f=72&t=100268
#    : http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0464f/ch10s06s01.html
 
adapter_khz 1000
adapter_nsrst_delay 400
reset_config none

gdb_breakpoint_override hard

if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME rpi2
}
 
#
# Main DAP
#
if { [info exists DAP_TAPID] } {
   set _DAP_TAPID $DAP_TAPID
} else {
   set _DAP_TAPID 0x4ba00477
}
jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x01 -irmask 0xf -expected-id $_DAP_TAPID
 
set _TARGETNAME $_CHIPNAME.cpu.0
target create $_TARGETNAME cortex_a -chain-position $_CHIPNAME.dap -coreid 0 -dbgbase 0x80010000
set _TARGETNAME $_CHIPNAME.cpu.1
target create $_TARGETNAME cortex_a -chain-position $_CHIPNAME.dap -coreid 1 -dbgbase 0x80012000
set _TARGETNAME $_CHIPNAME.cpu.2
target create $_TARGETNAME cortex_a -chain-position $_CHIPNAME.dap -coreid 2 -dbgbase 0x80014000
set _TARGETNAME $_CHIPNAME.cpu.3
target create $_TARGETNAME cortex_a -chain-position $_CHIPNAME.dap -coreid 3 -dbgbase 0x80016000
 
$_TARGETNAME configure -event reset-assert-post "cortex_a dbginit"
 
$_TARGETNAME configure -event gdb-attach { halt }
Run openocd

$ rmmod ftdi_sio usbserial
$ sudo src/openocd -f olimex-arm-usb-ocd-h.cfg -f openocd-rpi2.cfg 
[sudo] password for tono: 
Open On-Chip Debugger 0.9.0 (2015-07-16-17:40)
Licensed under GNU GPL v2
For bug reports, read
	http://openocd.org/doc/doxygen/bugs.html
Info : only one transport option; autoselect 'jtag'
adapter speed: 1000 kHz
adapter_nsrst_delay: 400
none separate
Warn : Using DEPRECATED interface driver 'ft2232'
Info : Consider using the 'ftdi' interface driver, with configuration files in interface/ftdi/...
Info : device: 6 "2232H"
Info : deviceID: 364511275
Info : SerialNumber: OLYPBH2QA
Info : Description: Olimex OpenOCD JTAG ARM-USB-OCD-H A
Info : max TCK change to: 30000 kHz
Info : clock speed 1000 kHz
Info : JTAG tap: rpi2.dap tap/device found: 0x4ba00477 (mfg: 0x23b, part: 0xba00, ver: 0x4)
Info : rpi2.cpu.0: hardware has 6 breakpoints, 4 watchpoints
Info : rpi2.cpu.1: hardware has 6 breakpoints, 4 watchpoints
Info : rpi2.cpu.2: hardware has 6 breakpoints, 4 watchpoints
Info : rpi2.cpu.3: hardware has 6 breakpoints, 4 watchpoints
Now connection established, you can see the brinking LED on top of ARM-USB-OCD-H.
connect to openocd server

open another terminal
$ telnet localhost 4444
Trying 127.0.0.1...
Connected to localhost.
Escape character is '^]'.
Open On-Chip Debugger
> halt                  
ttbcr 0ttbr0 ca5eaa5attbr1 fd7c7f73
rpi2.cpu.3 rev 5, partnum c07, arch f, variant 0, implementor 41
number of cache level 2
cache l2 present :not supported
rpi2.cpu.3 cluster f core 3 multi core
target state: halted
target halted in ARM state due to debug-request, current mode: Supervisor
cpsr: 0x600001d3 pc: 0x000000c4
MMU: disabled, D-Cache: disabled, I-Cache: disabled

connect to openocd server with using gdb

Download gcc-arm-none-eabi-4_9-2015q1-20150306-linux.tar.bz2 or later from here .

  
## rpi-jtag-pins.png

      
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              rpi-jtag-pins.png
Title	Holder
Cortex-A7 MPCore Technical Reference Manual Revision: r0p5	Online document
ARM Architecture Reference Manual® ARMv7-A and ARMv7-R edition	DDI0406C_C_arm_architecture_reference_manual.pdf
ARM Quad A7 Core Rev 3.4, 18-08-2014	QA7_rev3.4.pdf
BCM2835 ARM Peripherals	BCM2835-ARM-Peripherals.pdf
Bits	Name	Val	Function
[18]	NS_SMP	1 = A write to ACTLR in Non-secure state can modify the value of the SMP bit. Other bits in the ACTLR are write-ignored.	Determines if the SMP bit of the Auxiliary Control Register (ACTLR) is writable in Non-secure state:
[17]	NS_L2ERR	1 = A write to L2ECTLR in Non-secure state can modify the value of the L2 AXI asynchronous error bit. Other bits in the L2ECTLR are write-ignored.	NS_L2ERR Determines if the L2 AXI asynchronous error bit of the L2 Extended Control Register (L2ECTLR), are writable in Non-secure state:
[15]	NSASEDIS	0 = A write to CPACR.ASEDIS in Non-secure state can modify that value.	Disable Non-secure Advanced SIMD functionality
[14]	NSD32DIS	0 = A write to CPACR.D32DIS in Non-secure state can modify that value.	Disable the Non-secure use of D16-D31 of the VFP register file
[11]	cp11	1 = Secure or Non-secure access to CPACR.cp11.	Non-secure access to coprocessor 11 enable
[10]	cp10	1 = Secure or Non-secure access to CPACR.cp11.	Non-secure access to coprocessor 10 enable
commit	on	is contained in v0.9.0?
arm_adi_v5: add Cortex-A7 peripheral IDs	2015-05-08	No
cortex_a: Add support for A7 MPCore	2015-01-10	Yes
History for
openocd/src/target/arm_adi_v5.c	v0.9.0	master
openocd/src/target/cortex_a.c	v0.9.0	master
Name	Register number	Offset	rpi2.cpu0	rpi2.cpu1	rpi2.cpu2	rpi2.cpu3	Type	Description
DBGBCR	80-95	0x140 - 0x17C	0x80010140 - 0x8001017C	0x80012140 - 0x8001217C	0x80014140 - 0x8001417C	0x80016140 - 0x8001617C	RW	DBGBCR, Breakpoint Control Registers on page C11-2213
DBGBVR	64-79	0x100 - 0x13C	0x80010100 - 0x8001013C	0x80012100 - 0x8001213C	0x80014100 - 0x8001413C	0x80016100 - 0x8001613C	RW	DBGBVR, Breakpoint Value Registers on page C11-2218
Register number	CRn	opc2	CRm	Access	Register name	Description
80-95	c0	5	c0-15	RW	DBGBCRm	Breakpoint Control
64-79	c0	4	c0-15	RW	DBGBVRm	Breakpoint Value
example	nemonic	OpenOCD command
Read DBGBCR3	`MRC p14, 0, r2, c0, c3, 5`	`rpi2.cpu3 arm mrc 14 0 0 3 5`
Read DBGBVR3	`MRC p14, 0, r2, c0, c3, 4`	`rpi2.cpu3 arm mrc 14 0 0 3 4`
Bits	Name	Val	Function
[12]	I	0b1	Instruction cache enable bit: This is a global enable bit for instruction caches, for memory accesses made in Hyp mode.
[2]	C	0b1	Cache enable bit. This is a global enable bit for data and unified caches, for memory accesses made in Hyp mode.
[1]	M	0b1	MMU enable bit. This is a global enable bit for the PL2 stage 1 MMU.
HTCR	bits	Meaning	RPi2 default	XVisor set to
ORGN0[11:10]	0b01	Ourter Write-Back Write-Allocate Cacheable	Ourter Write-Back Write-Allocate Cacheable	Ourter Write-Back Write-Allocate Cacheable
IRGN0[9:8]	0b00	Inner Non-cacheable	Inner Non-cacheable	Inner Write-Back Write-Alocate Cacheable
VTCR	bits	Meaning	RPi2 default	XVisor set to
ORGN0[11:10]	0b00	Ourter Non-cacheable	Ourter Non-cacheable	Outer Write-Back Write-Allocate Cacheable
IRGN0[9:8]	0b00	Inner Non-cacheable	Innver Wirte-Back no Write-Allocate Cacheable	Inner Write-Back Write-Alocate Cacheable