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@tzechienchu
tzechienchu / ac701.py
Created February 1, 2024 08:55
Litex include Riffa PCIE verilog
from migen import *
from migen.genlib.cdc import MultiReg
from litex.gen import *
from litex.soc.interconnect.csr import *
from litex.soc.integration.builder import *
from litex.build.generic_platform import *
from litex.build.xilinx import XilinxPlatform
@tzechienchu
tzechienchu / mpFirmata.py
Created January 18, 2023 08:40
Micropython Firmata from Neon22/micropython-firmata
#! usr/bin/python
### Firmata implementation for Micro Python
### Protocol defined here: http://firmata.org/wiki/Protocol
### Custom for each hardware port
### Define the PINS and COMMS dictionaries below for each hardware device
@tzechienchu
tzechienchu / external_verilog.py
Created January 5, 2023 07:35
I2C Design use External Verilog in Migen
import os
from migen import *
from migen.genlib.cdc import MultiReg
from litex.soc.interconnect.csr import *
from litex.soc.interconnect.csr_eventmanager import *
from litex.soc.integration.doc import AutoDoc, ModuleDoc
@tzechienchu
tzechienchu / SynToAsyncToDync.py
Created January 4, 2023 13:00
Turn async to sync
import functools
def force_async(fn):
'''
turns a sync function to async function using threads
'''
from concurrent.futures import ThreadPoolExecutor
import asyncio
pool = ThreadPoolExecutor()
@tzechienchu
tzechienchu / ECP5_IO.py
Created December 30, 2022 05:01
ECP5 IO Define
# ECP5 AsyncResetSynchronizer ----------------------------------------------------------------------
class LatticeECP5AsyncResetSynchronizerImpl(Module):
def __init__(self, cd, async_reset):
rst1 = Signal()
self.specials += [
Instance("FD1S3BX",
i_D = 0,
i_PD = async_reset,
i_CK = cd.clk,
@tzechienchu
tzechienchu / ice40_io.py
Created December 30, 2022 05:00
ICE40 IO Define
# iCE40 AsyncResetSynchronizer ---------------------------------------------------------------------
class LatticeiCE40AsyncResetSynchronizerImpl(Module):
def __init__(self, cd, async_reset):
rst1 = Signal()
self.specials += [
Instance("SB_DFFS",
i_D = 0,
i_S = async_reset,
i_C = cd.clk,
@tzechienchu
tzechienchu / I2CSlave.py
Last active December 16, 2022 03:19
Amaranth HDL I2C Slave via amaranth-community-unofficial
from amaranth import Signal, Module, Cat, Elaboratable, Record, Mux
from amaranth.hdl.rec import DIR_FANIN, DIR_FANOUT
from amaranth.hdl.ast import Rose, Fell
from amaranth.compat import TSTriple
from amaranth.lib.cdc import FFSynchronizer
class I2CTarget(Elaboratable):
"""
Simple I2C target.
@tzechienchu
tzechienchu / poisson.c
Created December 7, 2022 08:54
Generate Poisson
//Poisson function -- returns a single Poisson random variable
int funPoissonSingle(double lambda)
{
double exp_lambda = exp(-lambda); //constant for terminating loop
double randUni; //uniform variable
double prodUni; //product of uniform variables
int randPoisson; //Poisson variable
//initialize variables
randPoisson = -1;
@tzechienchu
tzechienchu / commutator_sim.py
Created December 7, 2022 06:58
Simulation Mouse + Motor Control
from machine import Pin, PWM
import time
import random
import uasyncio
t0 = 0
ref0 = 0
pinpwmin = Pin(5,Pin.IN)
pindir = Pin(6,Pin.IN)
@tzechienchu
tzechienchu / hx1k.pcf
Created December 6, 2022 03:57
icestick hx1k constrain file
# iCEstick constraint file
#
# red LEDs
set_io lpc_clk_led 99
# set_io rled1 99
set_io lpc_frame_led 98
# set_io rled2 98
set_io lpc_reset_led 97
# set_io rled3 97
set_io valid_lpc_output_led 96