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@tzechienchu
tzechienchu / ft245.PY
Created November 22, 2022 04:01
ft245 python read usb data
import sys
import ftd2xx as ftd
print(ftd.listDevices())
d = ftd.open(1)
print(d.getDeviceInfo())
d.resetDevice()
d.setBitMode(0xff, 0x40)
d.setUSBParameters(64*1024, 64*1024)
d.setFlowControl(ftd.defines.FLOW_RTS_CTS)
@tzechienchu
tzechienchu / IceZProg.c
Created November 21, 2022 04:51
ICE40 Programming C Code for Raspberry Pi
/*
* IceZProg -- Programmer and Debug Tool for the IcoZero Board
*
* Copyright (C) 2017 Clifford Wolf <clifford@clifford.at>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
@tzechienchu
tzechienchu / plot_wave_save_bin.py
Created November 18, 2022 06:55
Wave file to Bin for Embedded System
import wave
import numpy as np
import matplotlib.pyplot as plt
import array
wav_obj = wave.open('spike11K.wav', 'rb')
sample_freq = wav_obj.getframerate()
print(sample_freq)
n_samples = wav_obj.getnframes()
print(n_samples)
@tzechienchu
tzechienchu / ice40_pll.v
Last active October 26, 2022 09:51
ICE40 PLL Verilog
SB_PLL40_PAD #(
.FEEDBACK_PATH("SIMPLE"),
.PLLOUT_SELECT("GENCLK"),
.DIVR(4'b0000),
.DIVF(7'b1010100),
.DIVQ(3'b101),
.FILTER_RANGE(3'b001),
) SB_PLL40_CORE_inst (
.RESETB(1'b1),
.BYPASS(1'b0),
@tzechienchu
tzechienchu / rom_ice40.v
Created October 25, 2022 10:15
ICE40 ROM Verilog
module Rom (
input clk,
input [6:0] addr,
output reg [7:0] data);
reg [7:0] Rom [127:0];
initial $readmemh("Rom.data", Rom);
always @(posedge clk)
data <= Rom[addr];
@tzechienchu
tzechienchu / i2c_scan_rw_test.py
Created October 25, 2022 10:01
Pico Micropython as I2C Test for Scan and Read/Write
from machine import Pin, I2C
import binascii
def i2c_read(i2c,reg):
rx_buf = bytearray(1)
reg_add = bytearray(1)
reg_add[0] = reg
i2c.writeto(0x55, reg_add)
rx_buf = i2c.readfrom(0x55, 1)
return binascii.hexlify(rx_buf)
@tzechienchu
tzechienchu / TriState.v
Last active October 25, 2022 09:53
TriState IO on ICE40
SB_IO #(
.PIN_TYPE(6'b1010_01),
.PULLUP(1'b0)
) triState (
.PACKAGE_PIN(pin),
.OUTPUT_ENABLE(oe),
.D_OUT_0(dout),
.D_IN_0(din)
);
@tzechienchu
tzechienchu / random.v
Created September 30, 2022 10:21
Random Number Generator use Verilog
///////////////////////////////////////////////////////////////////////////////////////////////////
//
// File: random_pulse_generator.v
// File history:
// Version 1: 2015-03-24: Created
//
// Description:
//
// Poisson process generator.
// Generate Poisson process with desired inversed rate (number of clocks per hit).
@tzechienchu
tzechienchu / ad_dac.v
Created September 30, 2022 07:28
Analog Device DAC Driver use Verilog
//Analog Device DAC Driver
module ad_dac(
clk,
rst,
send,
valid,
tx_value,
channel,
command,
rx_value,
@tzechienchu
tzechienchu / st_rom.v
Created September 30, 2022 07:27
Use ROM as Stimulus (this is a sine wave output for SPI controller)
module st_rom(
clk,
rst,
run,
st_out
);
input wire clk;
input wire rst;
input wire run;