ICE40 PLL Verilog

ice40_pll.v

    SB_PLL40_PAD #(
       .FEEDBACK_PATH("SIMPLE"),
       .PLLOUT_SELECT("GENCLK"),
       .DIVR(4'b0000),
       .DIVF(7'b1010100),
       .DIVQ(3'b101),
       .FILTER_RANGE(3'b001),
     ) SB_PLL40_CORE_inst (
       .RESETB(1'b1),
       .BYPASS(1'b0),
       .PACKAGEPIN(clk),
       .PLLOUTCORE(clk_32mhz),
    );
   
   SB_PLL40_CORE #(
      .FEEDBACK_PATH("SIMPLE"),
      .PLLOUT_SELECT("GENCLK"),
      .DIVR(4'b0000),
      .DIVF(7'b0001111),
      .DIVQ(3'b101),
      .FILTER_RANGE(3'b100),
    ) SB_PLL40_CORE_inst (
      .RESETB(1'b1),
      .BYPASS(1'b0),
      .PLLOUTCORE(clk_24mhz),
      .REFERENCECLK(clk_48mhz)
   );