ICE40 ROM Verilog

rom_ice40.v

module Rom (
    input clk,
    input [6:0] addr,
    output reg [7:0] data);
    
    reg [7:0] Rom [127:0];
    initial $readmemh("Rom.data", Rom);

    always @(posedge clk)
        data <= Rom[addr];

endmodule