clockDivider

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;

entity clockDivide is
    Port (
    clk_in : in STD_LOGIC;
    clk_reset : in STD_LOGIC;
    clk_out: out STD_LOGIC_VECTOR (3 downto 0 )
     );  
end clockDivide;

architecture Behavioral of clockDivide is
   
    signal temp : STD_LOGIC_VECTOR (3 downto 0);
    signal count: integer range 0 to 100000000; --bunu integer yap, 1hz nin s?n?r?nda
     
begin
    requency_divider: process (clk_in,clk_reset) 
    begin
        if clk_reset = '1' then
         temp <= ( others => '0');
         count <= 0;
        elsif rising_edge(clk_in) then
            if (count = 100000000) then
               temp <= std_logic_vector( unsigned(temp) + 1 );  --kütüphaneye aritmetik operation ekle
               count <= 0;
            else
                count <= count +1;
            end if;
        end if;
    end process;
    
    clk_out <= temp;
end Behavioral;