clockDivide.vhd

----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date: 11/07/2016 01:22:46 PM
-- Design Name: 
-- Module Name: clockDivide - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
----------------------------------------------------------------------------------
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;

entity clockDivide is
    Port (
    clk_in : in STD_LOGIC;
    clk_out: out STD_LOGIC_VECTOR (3 downto 0 )
     );  
end clockDivide;

architecture Behavioral of clockDivide is
   
    signal temp : STD_LOGIC_VECTOR (3 downto 0);
    signal count: integer range 0 to 50000000; --bunu integer yap, 1hz nin sınırında
     
begin
    requency_divider: process (clk_in) 
    begin
        if rising_edge(clk_in) then
            if (count = 50000000) then
                temp <= std_logic_vector( unsigned(temp) + 1 );  --kütüphaneye aritmetik operation ekle
                count <= 0;
            else
                count <= count +1;
            end if;
        end if;
    end process;
    
    clk_out <= temp;
end Behavioral;

Cons.xdc

set_property PACKAGE_PIN W5 [get_ports {default_Clock_Top}]
    set_property IOSTANDARD LVCMOS33 [get_ports {default_Clock_Top}]      
set_property PACKAGE_PIN L1 [get_ports {Custom_Clock_Top(3)}]
    set_property IOSTANDARD LVCMOS33 [get_ports {Custom_Clock_Top(3)}]
set_property PACKAGE_PIN P1 [get_ports {Custom_Clock_Top(2)}]
    set_property IOSTANDARD LVCMOS33 [get_ports {Custom_Clock_Top(2)}]
set_property PACKAGE_PIN N3 [get_ports {Custom_Clock_Top(1)}]
    set_property IOSTANDARD LVCMOS33 [get_ports {Custom_Clock_Top(1)}]
set_property PACKAGE_PIN P3 [get_ports {Custom_Clock_Top(0)}]
    set_property IOSTANDARD LVCMOS33 [get_ports {Custom_Clock_Top(0)}]   
    

mother.vhd

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity mother is
    port(
        default_clock_top : in std_logic;
        custom_clock_top : out std_logic_vector (3 downto 0)
        );
 end mother;
 
 architecture bhv of mother is
    component clockDivide --defining the inner clock module
        port( 
        clk_in : in std_logic;
        clk_out : out std_logic_vector (3 downto 0));
    end component; 
    signal A,B,C,D : std_logic ;
begin 
    ClockModule : clockDivide port map ( clk_in => default_clock_top, clk_out=>custom_clock_top);           
    --initialising the inner clock module
    custom_clock_top(0) <= D;
    custom_clock_top(1) <= C;
    custom_clock_top(2) <= B;
    custom_clock_top(3) <= A;
end bhv; 

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;

entity clockDivide is
Port (
clk_in : in STD_LOGIC;
clk_out: out STD_LOGIC_VECTOR (3 downto 0 )
);
end clockDivide;

architecture Behavioral of clockDivide is

signal temp : STD_LOGIC_VECTOR (3 downto 0);
signal count: integer range 0 to 50000000; --bunu integer yap, 1hz nin sınırında

begin
requency_divider: process (clk_in)
begin
if rising_edge(clk_in) then
if (count = 50000000) then
temp <= std_logic_vector( unsigned(temp) + 1 ); --kütüphaneye aritmetik operation ekle
count <= 0;
else
count <= count +1;
end if;
end if;
end process;

clk_out <= temp;

end Behavioral;

---

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity mother is
port(
default_clock_top : in std_logic;
custom_clock_top : out std_logic_vector (3 downto 0)
);
end mother;

architecture bhv of mother is
component clockDivide --defining the inner clock module
port(
clk_in : in std_logic;
clk_out : out std_logic_vector (3 downto 0));
end component;
--signal A,B,C,D : std_logic;
begin
--A <= '0';
--B<='0';
--c<='0';
--d<='0';

ClockModule : clockDivide port map ( clk_in => default_clock_top, clk_out=>custom_clock_top);           
--initialising the inner clock module
--custom_clock_top(0) <= D;
--custom_clock_top(1) <= C;
--custom_clock_top(2) <= B;
--custom_clock_top(3) <= A;

end bhv;

---

set_property PACKAGE_PIN W5 [get_ports {default_Clock_Top}]
set_property IOSTANDARD LVCMOS33 [get_ports {default_Clock_Top}]
set_property PACKAGE_PIN L1 [get_ports {Custom_Clock_Top[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Custom_Clock_Top[3]}]
set_property PACKAGE_PIN P1 [get_ports {Custom_Clock_Top[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Custom_Clock_Top[2]}]
set_property PACKAGE_PIN N3 [get_ports {Custom_Clock_Top[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Custom_Clock_Top[1]]}]
set_property PACKAGE_PIN P3 [get_ports {Custom_Clock_Top[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Custom_Clock_Top[0]}]