victor@accelerationrobotics:~/verilog-ethernet/example/KR260/fpga$ make
cd fpga && make
make[1]: Entering directory '/home/victor/verilog-ethernet/example/KR260/fpga/fpga'
echo "open_project fpga.xpr" > run_synth.tcl
echo "reset_run synth_1" >> run_synth.tcl
echo "launch_runs -jobs 4 synth_1" >> run_synth.tcl
echo "wait_on_run synth_1" >> run_synth.tcl
vivado -nojournal -nolog -mode batch -source run_synth.tcl
****** Vivado v2022.1 (64-bit)
**** SW Build 3526262 on Mon Apr 18 15:47:01 MDT 2022
**** IP Build 3524634 on Mon Apr 18 20:55:01 MDT 2022
** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
source run_synth.tcl
# open_project fpga.xpr
Scanning sources...
Finished scanning sources
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2022.1/data/ip'.
# reset_run synth_1
INFO: [Project 1-1161] Replacing file /home/victor/verilog-ethernet/example/KR260/fpga/fpga/fpga.srcs/utils_1/imports/synth_1/fpga.dcp with file /home/victor/verilog-ethernet/example/KR260/fpga/fpga/fpga.runs/synth_1/fpga.dcp
# launch_runs -jobs 4 synth_1
[Mon Mar 6 21:51:32 2023] Launched synth_1...
Run output will be captured here: /home/victor/verilog-ethernet/example/KR260/fpga/fpga/fpga.runs/synth_1/runme.log
# wait_on_run synth_1
[Mon Mar 6 21:51:32 2023] Waiting for synth_1 to finish...
*** Running vivado
with args -log fpga.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source fpga.tcl
****** Vivado v2022.1 (64-bit)
**** SW Build 3526262 on Mon Apr 18 15:47:01 MDT 2022
**** IP Build 3524634 on Mon Apr 18 20:55:01 MDT 2022
** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
source fpga.tcl -notrace
Command: read_checkpoint -auto_incremental -incremental /home/victor/verilog-ethernet/example/KR260/fpga/fpga/fpga.srcs/utils_1/imports/synth_1/fpga.dcp
INFO: [Vivado 12-5825] Read reference checkpoint from /home/victor/verilog-ethernet/example/KR260/fpga/fpga/fpga.srcs/utils_1/imports/synth_1/fpga.dcp for incremental synthesis
INFO: [Vivado 12-7989] Please ensure there are no constraint changes
Command: synth_design -top fpga -part xczu9eg-ffvb1156-2-e
Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xczu9eg'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xczu9eg'
INFO: [Common 17-86] Your Synthesis license expires in 15 day(s)
INFO: [Device 21-403] Loading part xczu9eg-ffvb1156-2-e
INFO: [Designutils 20-5440] No compile time benefit to using incremental synthesis; A full resynthesis will be run
INFO: [Designutils 20-4379] Flow is switching to default flow due to incremental criteria not met. If you would like to alter this behaviour and have the flow terminate instead, please set the following parameter config_implementation {autoIncr.Synth.RejectBehavior Terminate}
INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes.
INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
INFO: [Synth 8-7075] Helper process launched with PID 608257
WARNING: [Synth 8-9887] parameter declaration becomes local in 'arp_eth_rx' with formal parameter declaration list [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/rtl/arp_eth_rx.v:89]
WARNING: [Synth 8-9887] parameter declaration becomes local in 'arp_eth_rx' with formal parameter declaration list [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/rtl/arp_eth_rx.v:91]
WARNING: [Synth 8-9887] parameter declaration becomes local in 'arp_eth_rx' with formal parameter declaration list [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/rtl/arp_eth_rx.v:93]
WARNING: [Synth 8-9887] parameter declaration becomes local in 'arp_eth_tx' with formal parameter declaration list [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/rtl/arp_eth_tx.v:85]
WARNING: [Synth 8-9887] parameter declaration becomes local in 'arp_eth_tx' with formal parameter declaration list [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/rtl/arp_eth_tx.v:87]
WARNING: [Synth 8-9887] parameter declaration becomes local in 'arp_eth_tx' with formal parameter declaration list [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/rtl/arp_eth_tx.v:89]
WARNING: [Synth 8-9887] parameter declaration becomes local in 'axis_async_fifo' with formal parameter declaration list [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/lib/axis/rtl/axis_async_fifo.v:125]
WARNING: [Synth 8-9887] parameter declaration becomes local in 'axis_async_fifo' with formal parameter declaration list [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/lib/axis/rtl/axis_async_fifo.v:127]
WARNING: [Synth 8-9887] parameter declaration becomes local in 'axis_async_fifo_adapter' with formal parameter declaration list [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v:131]
WARNING: [Synth 8-9887] parameter declaration becomes local in 'axis_async_fifo_adapter' with formal parameter declaration list [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v:132]
WARNING: [Synth 8-9887] parameter declaration becomes local in 'axis_async_fifo_adapter' with formal parameter declaration list [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v:135]
WARNING: [Synth 8-9887] parameter declaration becomes local in 'axis_async_fifo_adapter' with formal parameter declaration list [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v:136]
WARNING: [Synth 8-9887] parameter declaration becomes local in 'axis_async_fifo_adapter' with formal parameter declaration list [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v:138]
WARNING: [Synth 8-9887] parameter declaration becomes local in 'axis_async_fifo_adapter' with formal parameter declaration list [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v:140]
WARNING: [Synth 8-9887] parameter declaration becomes local in 'axis_async_fifo_adapter' with formal parameter declaration list [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v:141]
WARNING: [Synth 8-9887] parameter declaration becomes local in 'axis_fifo' with formal parameter declaration list [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/lib/axis/rtl/axis_fifo.v:121]
WARNING: [Synth 8-9887] parameter declaration becomes local in 'axis_fifo' with formal parameter declaration list [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/lib/axis/rtl/axis_fifo.v:123]
WARNING: [Synth 8-9887] parameter declaration becomes local in 'axis_xgmii_tx_64' with formal parameter declaration list [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/rtl/axis_xgmii_tx_64.v:90]
WARNING: [Synth 8-9887] parameter declaration becomes local in 'axis_xgmii_tx_64' with formal parameter declaration list [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/rtl/axis_xgmii_tx_64.v:91]
WARNING: [Synth 8-9887] parameter declaration becomes local in 'eth_arb_mux' with formal parameter declaration list [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/rtl/eth_arb_mux.v:90]
WARNING: [Synth 8-9887] parameter declaration becomes local in 'eth_axis_rx' with formal parameter declaration list [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/rtl/eth_axis_rx.v:80]
WARNING: [Synth 8-9887] parameter declaration becomes local in 'eth_axis_rx' with formal parameter declaration list [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/rtl/eth_axis_rx.v:82]
WARNING: [Synth 8-9887] parameter declaration becomes local in 'eth_axis_rx' with formal parameter declaration list [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/rtl/eth_axis_rx.v:84]
WARNING: [Synth 8-9887] parameter declaration becomes local in 'eth_axis_tx' with formal parameter declaration list [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/rtl/eth_axis_tx.v:79]
WARNING: [Synth 8-9887] parameter declaration becomes local in 'eth_axis_tx' with formal parameter declaration list [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/rtl/eth_axis_tx.v:81]
WARNING: [Synth 8-9887] parameter declaration becomes local in 'eth_axis_tx' with formal parameter declaration list [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/rtl/eth_axis_tx.v:83]
WARNING: [Synth 8-9887] parameter declaration becomes local in 'eth_mac_10g_fifo' with formal parameter declaration list [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/rtl/eth_mac_10g_fifo.v:138]
WARNING: [Synth 8-9887] parameter declaration becomes local in 'eth_phy_10g_rx_ber_mon' with formal parameter declaration list [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/rtl/eth_phy_10g_rx_ber_mon.v:62]
WARNING: [Synth 8-9887] parameter declaration becomes local in 'eth_phy_10g_rx_frame_sync' with formal parameter declaration list [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/rtl/eth_phy_10g_rx_frame_sync.v:56]
WARNING: [Synth 8-9887] parameter declaration becomes local in 'eth_phy_10g_rx_frame_sync' with formal parameter declaration list [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/rtl/eth_phy_10g_rx_frame_sync.v:57]
WARNING: [Synth 8-9887] parameter declaration becomes local in 'eth_phy_10g_rx_watchdog' with formal parameter declaration list [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/rtl/eth_phy_10g_rx_watchdog.v:71]
WARNING: [Synth 8-9887] parameter declaration becomes local in 'ip_arb_mux' with formal parameter declaration list [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/rtl/ip_arb_mux.v:116]
WARNING: [Synth 8-9887] parameter declaration becomes local in 'lfsr' with formal parameter declaration list [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/rtl/lfsr.v:355]
WARNING: [Synth 8-9887] parameter declaration becomes local in 'priority_encoder' with formal parameter declaration list [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/lib/axis/rtl/priority_encoder.v:47]
WARNING: [Synth 8-9887] parameter declaration becomes local in 'priority_encoder' with formal parameter declaration list [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/lib/axis/rtl/priority_encoder.v:48]
WARNING: [Synth 8-9887] parameter declaration becomes local in 'udp_checksum_gen_64' with formal parameter declaration list [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/rtl/udp_checksum_gen_64.v:145]
---------------------------------------------------------------------------------
Starting RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2922.508 ; gain = 208.828 ; free physical = 43093 ; free virtual = 60967
---------------------------------------------------------------------------------
INFO: [Synth 8-6157] synthesizing module 'fpga' [/home/victor/verilog-ethernet/example/KR260/fpga/rtl/fpga.v:35]
INFO: [Synth 8-6157] synthesizing module 'IBUFGDS' [/tools/Xilinx/Vivado/2022.1/scripts/rt/data/unisim_comp.v:55701]
Parameter DIFF_TERM bound to: FALSE - type: string
Parameter IBUF_LOW_PWR bound to: FALSE - type: string
INFO: [Synth 8-6155] done synthesizing module 'IBUFGDS' (0#1) [/tools/Xilinx/Vivado/2022.1/scripts/rt/data/unisim_comp.v:55701]
INFO: [Synth 8-6157] synthesizing module 'BUFG' [/tools/Xilinx/Vivado/2022.1/scripts/rt/data/unisim_comp.v:1082]
INFO: [Synth 8-6155] done synthesizing module 'BUFG' (0#1) [/tools/Xilinx/Vivado/2022.1/scripts/rt/data/unisim_comp.v:1082]
INFO: [Synth 8-6157] synthesizing module 'MMCME4_BASE' [/tools/Xilinx/Vivado/2022.1/scripts/rt/data/unisim_comp.v:64029]
Parameter BANDWIDTH bound to: OPTIMIZED - type: string
Parameter CLKFBOUT_MULT_F bound to: 8.000000 - type: double
Parameter CLKFBOUT_PHASE bound to: 0.000000 - type: double
Parameter CLKIN1_PERIOD bound to: 8.000000 - type: double
Parameter CLKOUT0_DIVIDE_F bound to: 8.000000 - type: double
Parameter CLKOUT0_DUTY_CYCLE bound to: 0.500000 - type: double
Parameter CLKOUT0_PHASE bound to: 0.000000 - type: double
Parameter CLKOUT1_DIVIDE bound to: 1 - type: integer
Parameter CLKOUT1_DUTY_CYCLE bound to: 0.500000 - type: double
Parameter CLKOUT1_PHASE bound to: 0.000000 - type: double
Parameter CLKOUT2_DIVIDE bound to: 1 - type: integer
Parameter CLKOUT2_DUTY_CYCLE bound to: 0.500000 - type: double
Parameter CLKOUT2_PHASE bound to: 0.000000 - type: double
Parameter CLKOUT3_DIVIDE bound to: 1 - type: integer
Parameter CLKOUT3_DUTY_CYCLE bound to: 0.500000 - type: double
Parameter CLKOUT3_PHASE bound to: 0.000000 - type: double
Parameter CLKOUT4_CASCADE bound to: FALSE - type: string
Parameter CLKOUT4_DIVIDE bound to: 1 - type: integer
Parameter CLKOUT4_DUTY_CYCLE bound to: 0.500000 - type: double
Parameter CLKOUT4_PHASE bound to: 0.000000 - type: double
Parameter CLKOUT5_DIVIDE bound to: 1 - type: integer
Parameter CLKOUT5_DUTY_CYCLE bound to: 0.500000 - type: double
Parameter CLKOUT5_PHASE bound to: 0.000000 - type: double
Parameter CLKOUT6_DIVIDE bound to: 1 - type: integer
Parameter CLKOUT6_DUTY_CYCLE bound to: 0.500000 - type: double
Parameter CLKOUT6_PHASE bound to: 0.000000 - type: double
Parameter DIVCLK_DIVIDE bound to: 1 - type: integer
Parameter REF_JITTER1 bound to: 0.010000 - type: double
Parameter STARTUP_WAIT bound to: FALSE - type: string
INFO: [Synth 8-6155] done synthesizing module 'MMCME4_BASE' (0#1) [/tools/Xilinx/Vivado/2022.1/scripts/rt/data/unisim_comp.v:64029]
INFO: [Synth 8-6157] synthesizing module 'sync_reset' [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/lib/axis/rtl/sync_reset.v:35]
Parameter N bound to: 4 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'sync_reset' (0#1) [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/lib/axis/rtl/sync_reset.v:35]
INFO: [Synth 8-6157] synthesizing module 'IBUFDS_GTE4' [/tools/Xilinx/Vivado/2022.1/scripts/rt/data/unisim_comp.v:55395]
INFO: [Synth 8-6155] done synthesizing module 'IBUFDS_GTE4' (0#1) [/tools/Xilinx/Vivado/2022.1/scripts/rt/data/unisim_comp.v:55395]
INFO: [Synth 8-6157] synthesizing module 'eth_xcvr_phy_wrapper' [/home/victor/verilog-ethernet/example/KR260/fpga/rtl/eth_xcvr_phy_wrapper.v:34]
Parameter HAS_COMMON bound to: 1 - type: integer
INFO: [Synth 8-6157] synthesizing module 'eth_xcvr_gt_full' [/home/victor/verilog-ethernet/example/KR260/fpga/fpga/fpga.runs/synth_1/.Xil/Vivado-608251-accelerationrobotics/realtime/eth_xcvr_gt_full_stub.v:5]
INFO: [Synth 8-6155] done synthesizing module 'eth_xcvr_gt_full' (0#1) [/home/victor/verilog-ethernet/example/KR260/fpga/fpga/fpga.runs/synth_1/.Xil/Vivado-608251-accelerationrobotics/realtime/eth_xcvr_gt_full_stub.v:5]
INFO: [Synth 8-6157] synthesizing module 'eth_phy_10g' [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/rtl/eth_phy_10g.v:34]
Parameter DATA_WIDTH bound to: 64 - type: integer
Parameter CTRL_WIDTH bound to: 8 - type: integer
Parameter HDR_WIDTH bound to: 2 - type: integer
Parameter BIT_REVERSE bound to: 1 - type: integer
Parameter SCRAMBLER_DISABLE bound to: 0 - type: integer
Parameter PRBS31_ENABLE bound to: 0 - type: integer
Parameter TX_SERDES_PIPELINE bound to: 0 - type: integer
Parameter RX_SERDES_PIPELINE bound to: 0 - type: integer
Parameter BITSLIP_HIGH_CYCLES bound to: 1 - type: integer
Parameter BITSLIP_LOW_CYCLES bound to: 8 - type: integer
Parameter COUNT_125US bound to: 19531.250000 - type: double
INFO: [Synth 8-6157] synthesizing module 'eth_phy_10g_rx' [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/rtl/eth_phy_10g_rx.v:34]
Parameter DATA_WIDTH bound to: 64 - type: integer
Parameter CTRL_WIDTH bound to: 8 - type: integer
Parameter HDR_WIDTH bound to: 2 - type: integer
Parameter BIT_REVERSE bound to: 1 - type: integer
Parameter SCRAMBLER_DISABLE bound to: 0 - type: integer
Parameter PRBS31_ENABLE bound to: 0 - type: integer
Parameter SERDES_PIPELINE bound to: 0 - type: integer
Parameter BITSLIP_HIGH_CYCLES bound to: 1 - type: integer
Parameter BITSLIP_LOW_CYCLES bound to: 8 - type: integer
Parameter COUNT_125US bound to: 19531.250000 - type: double
INFO: [Synth 8-6157] synthesizing module 'eth_phy_10g_rx_if' [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/rtl/eth_phy_10g_rx_if.v:34]
Parameter DATA_WIDTH bound to: 64 - type: integer
Parameter HDR_WIDTH bound to: 2 - type: integer
Parameter BIT_REVERSE bound to: 1 - type: integer
Parameter SCRAMBLER_DISABLE bound to: 0 - type: integer
Parameter PRBS31_ENABLE bound to: 0 - type: integer
Parameter SERDES_PIPELINE bound to: 0 - type: integer
Parameter BITSLIP_HIGH_CYCLES bound to: 1 - type: integer
Parameter BITSLIP_LOW_CYCLES bound to: 8 - type: integer
Parameter COUNT_125US bound to: 19531.250000 - type: double
INFO: [Synth 8-6157] synthesizing module 'lfsr' [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/rtl/lfsr.v:34]
Parameter LFSR_WIDTH bound to: 58 - type: integer
Parameter LFSR_POLY bound to: 58'b0000000000000000001000000000000000000000000000000000000001
Parameter LFSR_CONFIG bound to: FIBONACCI - type: string
Parameter LFSR_FEED_FORWARD bound to: 1 - type: integer
Parameter REVERSE bound to: 1 - type: integer
Parameter DATA_WIDTH bound to: 64 - type: integer
Parameter STYLE bound to: AUTO - type: string
INFO: [Synth 8-6155] done synthesizing module 'lfsr' (0#1) [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/rtl/lfsr.v:34]
INFO: [Synth 8-6157] synthesizing module 'lfsr__parameterized0' [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/rtl/lfsr.v:34]
Parameter LFSR_WIDTH bound to: 31 - type: integer
Parameter LFSR_POLY bound to: 31'b0010000000000000000000000000001
Parameter LFSR_CONFIG bound to: FIBONACCI - type: string
Parameter LFSR_FEED_FORWARD bound to: 1 - type: integer
Parameter REVERSE bound to: 1 - type: integer
Parameter DATA_WIDTH bound to: 66 - type: integer
Parameter STYLE bound to: AUTO - type: string
INFO: [Synth 8-6155] done synthesizing module 'lfsr__parameterized0' (0#1) [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/rtl/lfsr.v:34]
INFO: [Synth 8-6157] synthesizing module 'eth_phy_10g_rx_frame_sync' [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/rtl/eth_phy_10g_rx_frame_sync.v:34]
Parameter HDR_WIDTH bound to: 2 - type: integer
Parameter BITSLIP_HIGH_CYCLES bound to: 1 - type: integer
Parameter BITSLIP_LOW_CYCLES bound to: 8 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'eth_phy_10g_rx_frame_sync' (0#1) [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/rtl/eth_phy_10g_rx_frame_sync.v:34]
INFO: [Synth 8-6157] synthesizing module 'eth_phy_10g_rx_ber_mon' [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/rtl/eth_phy_10g_rx_ber_mon.v:34]
Parameter HDR_WIDTH bound to: 2 - type: integer
Parameter COUNT_125US bound to: 19531.250000 - type: double
INFO: [Synth 8-6155] done synthesizing module 'eth_phy_10g_rx_ber_mon' (0#1) [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/rtl/eth_phy_10g_rx_ber_mon.v:34]
INFO: [Synth 8-6157] synthesizing module 'eth_phy_10g_rx_watchdog' [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/rtl/eth_phy_10g_rx_watchdog.v:34]
Parameter HDR_WIDTH bound to: 2 - type: integer
Parameter COUNT_125US bound to: 19531.250000 - type: double
INFO: [Synth 8-6155] done synthesizing module 'eth_phy_10g_rx_watchdog' (0#1) [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/rtl/eth_phy_10g_rx_watchdog.v:34]
INFO: [Synth 8-6155] done synthesizing module 'eth_phy_10g_rx_if' (0#1) [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/rtl/eth_phy_10g_rx_if.v:34]
INFO: [Synth 8-6157] synthesizing module 'xgmii_baser_dec_64' [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/rtl/xgmii_baser_dec_64.v:34]
Parameter DATA_WIDTH bound to: 64 - type: integer
Parameter CTRL_WIDTH bound to: 8 - type: integer
Parameter HDR_WIDTH bound to: 2 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'xgmii_baser_dec_64' (0#1) [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/rtl/xgmii_baser_dec_64.v:34]
INFO: [Synth 8-6155] done synthesizing module 'eth_phy_10g_rx' (0#1) [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/rtl/eth_phy_10g_rx.v:34]
INFO: [Synth 8-6157] synthesizing module 'eth_phy_10g_tx' [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/rtl/eth_phy_10g_tx.v:34]
Parameter DATA_WIDTH bound to: 64 - type: integer
Parameter CTRL_WIDTH bound to: 8 - type: integer
Parameter HDR_WIDTH bound to: 2 - type: integer
Parameter BIT_REVERSE bound to: 1 - type: integer
Parameter SCRAMBLER_DISABLE bound to: 0 - type: integer
Parameter PRBS31_ENABLE bound to: 0 - type: integer
Parameter SERDES_PIPELINE bound to: 0 - type: integer
INFO: [Synth 8-6157] synthesizing module 'xgmii_baser_enc_64' [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/rtl/xgmii_baser_enc_64.v:34]
Parameter DATA_WIDTH bound to: 64 - type: integer
Parameter CTRL_WIDTH bound to: 8 - type: integer
Parameter HDR_WIDTH bound to: 2 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'xgmii_baser_enc_64' (0#1) [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/rtl/xgmii_baser_enc_64.v:34]
INFO: [Synth 8-6157] synthesizing module 'eth_phy_10g_tx_if' [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/rtl/eth_phy_10g_tx_if.v:34]
Parameter DATA_WIDTH bound to: 64 - type: integer
Parameter HDR_WIDTH bound to: 2 - type: integer
Parameter BIT_REVERSE bound to: 1 - type: integer
Parameter SCRAMBLER_DISABLE bound to: 0 - type: integer
Parameter PRBS31_ENABLE bound to: 0 - type: integer
Parameter SERDES_PIPELINE bound to: 0 - type: integer
INFO: [Synth 8-6157] synthesizing module 'lfsr__parameterized1' [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/rtl/lfsr.v:34]
Parameter LFSR_WIDTH bound to: 58 - type: integer
Parameter LFSR_POLY bound to: 58'b0000000000000000001000000000000000000000000000000000000001
Parameter LFSR_CONFIG bound to: FIBONACCI - type: string
Parameter LFSR_FEED_FORWARD bound to: 0 - type: integer
Parameter REVERSE bound to: 1 - type: integer
Parameter DATA_WIDTH bound to: 64 - type: integer
Parameter STYLE bound to: AUTO - type: string
INFO: [Synth 8-6155] done synthesizing module 'lfsr__parameterized1' (0#1) [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/rtl/lfsr.v:34]
INFO: [Synth 8-6157] synthesizing module 'lfsr__parameterized2' [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/rtl/lfsr.v:34]
Parameter LFSR_WIDTH bound to: 31 - type: integer
Parameter LFSR_POLY bound to: 31'b0010000000000000000000000000001
Parameter LFSR_CONFIG bound to: FIBONACCI - type: string
Parameter LFSR_FEED_FORWARD bound to: 0 - type: integer
Parameter REVERSE bound to: 1 - type: integer
Parameter DATA_WIDTH bound to: 66 - type: integer
Parameter STYLE bound to: AUTO - type: string
INFO: [Synth 8-6155] done synthesizing module 'lfsr__parameterized2' (0#1) [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/rtl/lfsr.v:34]
INFO: [Synth 8-6155] done synthesizing module 'eth_phy_10g_tx_if' (0#1) [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/rtl/eth_phy_10g_tx_if.v:34]
INFO: [Synth 8-6155] done synthesizing module 'eth_phy_10g_tx' (0#1) [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/rtl/eth_phy_10g_tx.v:34]
INFO: [Synth 8-6155] done synthesizing module 'eth_phy_10g' (0#1) [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/rtl/eth_phy_10g.v:34]
WARNING: [Synth 8-689] width (6) of port connection 'serdes_tx_hdr' does not match port width (2) of module 'eth_phy_10g' [/home/victor/verilog-ethernet/example/KR260/fpga/rtl/eth_xcvr_phy_wrapper.v:282]
WARNING: [Synth 8-689] width (6) of port connection 'serdes_rx_hdr' does not match port width (2) of module 'eth_phy_10g' [/home/victor/verilog-ethernet/example/KR260/fpga/rtl/eth_xcvr_phy_wrapper.v:284]
WARNING: [Synth 8-7071] port 'rx_status' of module 'eth_phy_10g' is unconnected for instance 'phy_inst' [/home/victor/verilog-ethernet/example/KR260/fpga/rtl/eth_xcvr_phy_wrapper.v:272]
WARNING: [Synth 8-7023] instance 'phy_inst' of module 'eth_phy_10g' has 23 connections declared, but only 22 given [/home/victor/verilog-ethernet/example/KR260/fpga/rtl/eth_xcvr_phy_wrapper.v:272]
INFO: [Synth 8-6155] done synthesizing module 'eth_xcvr_phy_wrapper' (0#1) [/home/victor/verilog-ethernet/example/KR260/fpga/rtl/eth_xcvr_phy_wrapper.v:34]
INFO: [Synth 8-6157] synthesizing module 'fpga_core' [/home/victor/verilog-ethernet/example/KR260/fpga/rtl/fpga_core.v:35]
INFO: [Synth 8-6157] synthesizing module 'eth_mac_10g_fifo' [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/rtl/eth_mac_10g_fifo.v:34]
Parameter ENABLE_PADDING bound to: 1 - type: integer
Parameter ENABLE_DIC bound to: 1 - type: integer
Parameter MIN_FRAME_LENGTH bound to: 64 - type: integer
Parameter TX_FIFO_DEPTH bound to: 4096 - type: integer
Parameter TX_FRAME_FIFO bound to: 1 - type: integer
Parameter RX_FIFO_DEPTH bound to: 4096 - type: integer
Parameter RX_FRAME_FIFO bound to: 1 - type: integer
INFO: [Synth 8-6157] synthesizing module 'eth_mac_10g' [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/rtl/eth_mac_10g.v:34]
Parameter DATA_WIDTH bound to: 64 - type: integer
Parameter KEEP_WIDTH bound to: 8 - type: integer
Parameter CTRL_WIDTH bound to: 8 - type: integer
Parameter ENABLE_PADDING bound to: 1 - type: integer
Parameter ENABLE_DIC bound to: 1 - type: integer
Parameter MIN_FRAME_LENGTH bound to: 64 - type: integer
Parameter PTP_PERIOD_NS bound to: 4'b0110
Parameter PTP_PERIOD_FNS bound to: 16'b0110011001100110
Parameter TX_PTP_TS_ENABLE bound to: 0 - type: integer
Parameter TX_PTP_TS_WIDTH bound to: 96 - type: integer
Parameter TX_PTP_TAG_ENABLE bound to: 0 - type: integer
Parameter TX_PTP_TAG_WIDTH bound to: 16 - type: integer
Parameter RX_PTP_TS_ENABLE bound to: 0 - type: integer
Parameter RX_PTP_TS_WIDTH bound to: 96 - type: integer
Parameter TX_USER_WIDTH bound to: 1 - type: integer
Parameter RX_USER_WIDTH bound to: 1 - type: integer
INFO: [Synth 8-6157] synthesizing module 'axis_xgmii_rx_64' [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/rtl/axis_xgmii_rx_64.v:34]
Parameter DATA_WIDTH bound to: 64 - type: integer
Parameter KEEP_WIDTH bound to: 8 - type: integer
Parameter CTRL_WIDTH bound to: 8 - type: integer
Parameter PTP_PERIOD_NS bound to: 4'b0110
Parameter PTP_PERIOD_FNS bound to: 16'b0110011001100110
Parameter PTP_TS_ENABLE bound to: 0 - type: integer
Parameter PTP_TS_WIDTH bound to: 96 - type: integer
Parameter USER_WIDTH bound to: 1 - type: integer
INFO: [Synth 8-6157] synthesizing module 'lfsr__parameterized3' [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/rtl/lfsr.v:34]
Parameter LFSR_WIDTH bound to: 32 - type: integer
Parameter LFSR_POLY bound to: 79764919 - type: integer
Parameter LFSR_CONFIG bound to: GALOIS - type: string
Parameter LFSR_FEED_FORWARD bound to: 0 - type: integer
Parameter REVERSE bound to: 1 - type: integer
Parameter DATA_WIDTH bound to: 64 - type: integer
Parameter STYLE bound to: AUTO - type: string
INFO: [Synth 8-6155] done synthesizing module 'lfsr__parameterized3' (0#1) [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/rtl/lfsr.v:34]
INFO: [Synth 8-226] default block is never used [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/rtl/axis_xgmii_rx_64.v:207]
INFO: [Synth 8-155] case statement is not full and has no default [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/rtl/axis_xgmii_rx_64.v:268]
INFO: [Synth 8-6155] done synthesizing module 'axis_xgmii_rx_64' (0#1) [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/rtl/axis_xgmii_rx_64.v:34]
INFO: [Synth 8-6157] synthesizing module 'axis_xgmii_tx_64' [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/rtl/axis_xgmii_tx_64.v:34]
Parameter DATA_WIDTH bound to: 64 - type: integer
Parameter KEEP_WIDTH bound to: 8 - type: integer
Parameter CTRL_WIDTH bound to: 8 - type: integer
Parameter ENABLE_PADDING bound to: 1 - type: integer
Parameter ENABLE_DIC bound to: 1 - type: integer
Parameter MIN_FRAME_LENGTH bound to: 64 - type: integer
Parameter PTP_PERIOD_NS bound to: 4'b0110
Parameter PTP_PERIOD_FNS bound to: 16'b0110011001100110
Parameter PTP_TS_ENABLE bound to: 0 - type: integer
Parameter PTP_TS_WIDTH bound to: 96 - type: integer
Parameter PTP_TAG_ENABLE bound to: 0 - type: integer
Parameter PTP_TAG_WIDTH bound to: 16 - type: integer
Parameter USER_WIDTH bound to: 1 - type: integer
INFO: [Synth 8-6157] synthesizing module 'lfsr__parameterized4' [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/rtl/lfsr.v:34]
Parameter LFSR_WIDTH bound to: 32 - type: integer
Parameter LFSR_POLY bound to: 79764919 - type: integer
Parameter LFSR_CONFIG bound to: GALOIS - type: string
Parameter LFSR_FEED_FORWARD bound to: 0 - type: integer
Parameter REVERSE bound to: 1 - type: integer
Parameter DATA_WIDTH bound to: 8 - type: integer
Parameter STYLE bound to: AUTO - type: string
INFO: [Synth 8-6155] done synthesizing module 'lfsr__parameterized4' (0#1) [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/rtl/lfsr.v:34]
INFO: [Synth 8-6157] synthesizing module 'lfsr__parameterized5' [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/rtl/lfsr.v:34]
Parameter LFSR_WIDTH bound to: 32 - type: integer
Parameter LFSR_POLY bound to: 79764919 - type: integer
Parameter LFSR_CONFIG bound to: GALOIS - type: string
Parameter LFSR_FEED_FORWARD bound to: 0 - type: integer
Parameter REVERSE bound to: 1 - type: integer
Parameter DATA_WIDTH bound to: 16 - type: integer
Parameter STYLE bound to: AUTO - type: string
INFO: [Synth 8-6155] done synthesizing module 'lfsr__parameterized5' (0#1) [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/rtl/lfsr.v:34]
INFO: [Synth 8-6157] synthesizing module 'lfsr__parameterized6' [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/rtl/lfsr.v:34]
Parameter LFSR_WIDTH bound to: 32 - type: integer
Parameter LFSR_POLY bound to: 79764919 - type: integer
Parameter LFSR_CONFIG bound to: GALOIS - type: string
Parameter LFSR_FEED_FORWARD bound to: 0 - type: integer
Parameter REVERSE bound to: 1 - type: integer
Parameter DATA_WIDTH bound to: 24 - type: integer
Parameter STYLE bound to: AUTO - type: string
INFO: [Synth 8-6155] done synthesizing module 'lfsr__parameterized6' (0#1) [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/rtl/lfsr.v:34]
INFO: [Synth 8-6157] synthesizing module 'lfsr__parameterized7' [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/rtl/lfsr.v:34]
Parameter LFSR_WIDTH bound to: 32 - type: integer
Parameter LFSR_POLY bound to: 79764919 - type: integer
Parameter LFSR_CONFIG bound to: GALOIS - type: string
Parameter LFSR_FEED_FORWARD bound to: 0 - type: integer
Parameter REVERSE bound to: 1 - type: integer
Parameter DATA_WIDTH bound to: 32 - type: integer
Parameter STYLE bound to: AUTO - type: string
INFO: [Synth 8-6155] done synthesizing module 'lfsr__parameterized7' (0#1) [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/rtl/lfsr.v:34]
INFO: [Synth 8-6157] synthesizing module 'lfsr__parameterized8' [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/rtl/lfsr.v:34]
Parameter LFSR_WIDTH bound to: 32 - type: integer
Parameter LFSR_POLY bound to: 79764919 - type: integer
Parameter LFSR_CONFIG bound to: GALOIS - type: string
Parameter LFSR_FEED_FORWARD bound to: 0 - type: integer
Parameter REVERSE bound to: 1 - type: integer
Parameter DATA_WIDTH bound to: 40 - type: integer
Parameter STYLE bound to: AUTO - type: string
INFO: [Synth 8-6155] done synthesizing module 'lfsr__parameterized8' (0#1) [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/rtl/lfsr.v:34]
INFO: [Synth 8-6157] synthesizing module 'lfsr__parameterized9' [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/rtl/lfsr.v:34]
Parameter LFSR_WIDTH bound to: 32 - type: integer
Parameter LFSR_POLY bound to: 79764919 - type: integer
Parameter LFSR_CONFIG bound to: GALOIS - type: string
Parameter LFSR_FEED_FORWARD bound to: 0 - type: integer
Parameter REVERSE bound to: 1 - type: integer
Parameter DATA_WIDTH bound to: 48 - type: integer
Parameter STYLE bound to: AUTO - type: string
INFO: [Synth 8-6155] done synthesizing module 'lfsr__parameterized9' (0#1) [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/rtl/lfsr.v:34]
INFO: [Synth 8-6157] synthesizing module 'lfsr__parameterized10' [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/rtl/lfsr.v:34]
Parameter LFSR_WIDTH bound to: 32 - type: integer
Parameter LFSR_POLY bound to: 79764919 - type: integer
Parameter LFSR_CONFIG bound to: GALOIS - type: string
Parameter LFSR_FEED_FORWARD bound to: 0 - type: integer
Parameter REVERSE bound to: 1 - type: integer
Parameter DATA_WIDTH bound to: 56 - type: integer
Parameter STYLE bound to: AUTO - type: string
INFO: [Synth 8-6155] done synthesizing module 'lfsr__parameterized10' (0#1) [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/rtl/lfsr.v:34]
INFO: [Synth 8-155] case statement is not full and has no default [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/rtl/axis_xgmii_tx_64.v:332]
INFO: [Synth 8-6155] done synthesizing module 'axis_xgmii_tx_64' (0#1) [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/rtl/axis_xgmii_tx_64.v:34]
INFO: [Synth 8-6155] done synthesizing module 'eth_mac_10g' (0#1) [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/rtl/eth_mac_10g.v:34]
WARNING: [Synth 8-7071] port 'tx_start_packet' of module 'eth_mac_10g' is unconnected for instance 'eth_mac_10g_inst' [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/rtl/eth_mac_10g_fifo.v:349]
WARNING: [Synth 8-7071] port 'rx_start_packet' of module 'eth_mac_10g' is unconnected for instance 'eth_mac_10g_inst' [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/rtl/eth_mac_10g_fifo.v:349]
WARNING: [Synth 8-7023] instance 'eth_mac_10g_inst' of module 'eth_mac_10g' has 30 connections declared, but only 28 given [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/rtl/eth_mac_10g_fifo.v:349]
INFO: [Synth 8-6157] synthesizing module 'axis_async_fifo_adapter' [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v:34]
Parameter DEPTH bound to: 4096 - type: integer
Parameter S_DATA_WIDTH bound to: 64 - type: integer
Parameter S_KEEP_ENABLE bound to: 1'b1
Parameter S_KEEP_WIDTH bound to: 8 - type: integer
Parameter M_DATA_WIDTH bound to: 64 - type: integer
Parameter M_KEEP_ENABLE bound to: 1 - type: integer
Parameter M_KEEP_WIDTH bound to: 8 - type: integer
Parameter ID_ENABLE bound to: 0 - type: integer
Parameter DEST_ENABLE bound to: 0 - type: integer
Parameter USER_ENABLE bound to: 1 - type: integer
Parameter USER_WIDTH bound to: 1 - type: integer
Parameter RAM_PIPELINE bound to: 1 - type: integer
Parameter FRAME_FIFO bound to: 1 - type: integer
Parameter USER_BAD_FRAME_VALUE bound to: 1'b1
Parameter USER_BAD_FRAME_MASK bound to: 1'b1
Parameter DROP_OVERSIZE_FRAME bound to: 1 - type: integer
Parameter DROP_BAD_FRAME bound to: 1 - type: integer
Parameter DROP_WHEN_FULL bound to: 0 - type: integer
INFO: [Synth 8-6157] synthesizing module 'axis_async_fifo' [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/lib/axis/rtl/axis_async_fifo.v:34]
Parameter DEPTH bound to: 4096 - type: integer
Parameter DATA_WIDTH bound to: 64 - type: integer
Parameter KEEP_ENABLE bound to: 1 - type: integer
Parameter KEEP_WIDTH bound to: 8 - type: integer
Parameter LAST_ENABLE bound to: 1 - type: integer
Parameter ID_ENABLE bound to: 0 - type: integer
Parameter ID_WIDTH bound to: 8 - type: integer
Parameter DEST_ENABLE bound to: 0 - type: integer
Parameter DEST_WIDTH bound to: 8 - type: integer
Parameter USER_ENABLE bound to: 1 - type: integer
Parameter USER_WIDTH bound to: 1 - type: integer
Parameter RAM_PIPELINE bound to: 1 - type: integer
Parameter OUTPUT_FIFO_ENABLE bound to: 0 - type: integer
Parameter FRAME_FIFO bound to: 1 - type: integer
Parameter USER_BAD_FRAME_VALUE bound to: 1'b1
Parameter USER_BAD_FRAME_MASK bound to: 1'b1
Parameter DROP_OVERSIZE_FRAME bound to: 1 - type: integer
Parameter DROP_BAD_FRAME bound to: 1 - type: integer
Parameter DROP_WHEN_FULL bound to: 0 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'axis_async_fifo' (0#1) [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/lib/axis/rtl/axis_async_fifo.v:34]
INFO: [Synth 8-6155] done synthesizing module 'axis_async_fifo_adapter' (0#1) [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v:34]
INFO: [Synth 8-6157] synthesizing module 'axis_async_fifo_adapter__parameterized0' [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v:34]
Parameter DEPTH bound to: 4096 - type: integer
Parameter S_DATA_WIDTH bound to: 64 - type: integer
Parameter S_KEEP_ENABLE bound to: 1 - type: integer
Parameter S_KEEP_WIDTH bound to: 8 - type: integer
Parameter M_DATA_WIDTH bound to: 64 - type: integer
Parameter M_KEEP_ENABLE bound to: 1'b1
Parameter M_KEEP_WIDTH bound to: 8 - type: integer
Parameter ID_ENABLE bound to: 0 - type: integer
Parameter DEST_ENABLE bound to: 0 - type: integer
Parameter USER_ENABLE bound to: 1 - type: integer
Parameter USER_WIDTH bound to: 1 - type: integer
Parameter RAM_PIPELINE bound to: 1 - type: integer
Parameter FRAME_FIFO bound to: 1 - type: integer
Parameter USER_BAD_FRAME_VALUE bound to: 1'b1
Parameter USER_BAD_FRAME_MASK bound to: 1'b1
Parameter DROP_OVERSIZE_FRAME bound to: 1 - type: integer
Parameter DROP_BAD_FRAME bound to: 1 - type: integer
Parameter DROP_WHEN_FULL bound to: 1 - type: integer
INFO: [Synth 8-6157] synthesizing module 'axis_async_fifo__parameterized0' [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/lib/axis/rtl/axis_async_fifo.v:34]
Parameter DEPTH bound to: 4096 - type: integer
Parameter DATA_WIDTH bound to: 64 - type: integer
Parameter KEEP_ENABLE bound to: 1 - type: integer
Parameter KEEP_WIDTH bound to: 8 - type: integer
Parameter LAST_ENABLE bound to: 1 - type: integer
Parameter ID_ENABLE bound to: 0 - type: integer
Parameter ID_WIDTH bound to: 8 - type: integer
Parameter DEST_ENABLE bound to: 0 - type: integer
Parameter DEST_WIDTH bound to: 8 - type: integer
Parameter USER_ENABLE bound to: 1 - type: integer
Parameter USER_WIDTH bound to: 1 - type: integer
Parameter RAM_PIPELINE bound to: 1 - type: integer
Parameter OUTPUT_FIFO_ENABLE bound to: 0 - type: integer
Parameter FRAME_FIFO bound to: 1 - type: integer
Parameter USER_BAD_FRAME_VALUE bound to: 1'b1
Parameter USER_BAD_FRAME_MASK bound to: 1'b1
Parameter DROP_OVERSIZE_FRAME bound to: 1 - type: integer
Parameter DROP_BAD_FRAME bound to: 1 - type: integer
Parameter DROP_WHEN_FULL bound to: 1 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'axis_async_fifo__parameterized0' (0#1) [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/lib/axis/rtl/axis_async_fifo.v:34]
INFO: [Synth 8-6155] done synthesizing module 'axis_async_fifo_adapter__parameterized0' (0#1) [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v:34]
INFO: [Synth 8-6155] done synthesizing module 'eth_mac_10g_fifo' (0#1) [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/rtl/eth_mac_10g_fifo.v:34]
WARNING: [Synth 8-7071] port 'ptp_sample_clk' of module 'eth_mac_10g_fifo' is unconnected for instance 'eth_mac_10g_fifo_inst' [/home/victor/verilog-ethernet/example/KR260/fpga/rtl/fpga_core.v:352]
WARNING: [Synth 8-7071] port 'm_axis_tx_ptp_ts_96' of module 'eth_mac_10g_fifo' is unconnected for instance 'eth_mac_10g_fifo_inst' [/home/victor/verilog-ethernet/example/KR260/fpga/rtl/fpga_core.v:352]
WARNING: [Synth 8-7071] port 'm_axis_tx_ptp_ts_tag' of module 'eth_mac_10g_fifo' is unconnected for instance 'eth_mac_10g_fifo_inst' [/home/victor/verilog-ethernet/example/KR260/fpga/rtl/fpga_core.v:352]
WARNING: [Synth 8-7071] port 'm_axis_tx_ptp_ts_valid' of module 'eth_mac_10g_fifo' is unconnected for instance 'eth_mac_10g_fifo_inst' [/home/victor/verilog-ethernet/example/KR260/fpga/rtl/fpga_core.v:352]
WARNING: [Synth 8-7071] port 'm_axis_tx_ptp_ts_ready' of module 'eth_mac_10g_fifo' is unconnected for instance 'eth_mac_10g_fifo_inst' [/home/victor/verilog-ethernet/example/KR260/fpga/rtl/fpga_core.v:352]
WARNING: [Synth 8-7071] port 'tx_error_underflow' of module 'eth_mac_10g_fifo' is unconnected for instance 'eth_mac_10g_fifo_inst' [/home/victor/verilog-ethernet/example/KR260/fpga/rtl/fpga_core.v:352]
WARNING: [Synth 8-7071] port 'ptp_ts_96' of module 'eth_mac_10g_fifo' is unconnected for instance 'eth_mac_10g_fifo_inst' [/home/victor/verilog-ethernet/example/KR260/fpga/rtl/fpga_core.v:352]
WARNING: [Synth 8-7071] port 'ptp_ts_step' of module 'eth_mac_10g_fifo' is unconnected for instance 'eth_mac_10g_fifo_inst' [/home/victor/verilog-ethernet/example/KR260/fpga/rtl/fpga_core.v:352]
WARNING: [Synth 8-7023] instance 'eth_mac_10g_fifo_inst' of module 'eth_mac_10g_fifo' has 39 connections declared, but only 31 given [/home/victor/verilog-ethernet/example/KR260/fpga/rtl/fpga_core.v:352]
INFO: [Synth 8-6157] synthesizing module 'eth_axis_rx' [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/rtl/eth_axis_rx.v:34]
Parameter DATA_WIDTH bound to: 64 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'eth_axis_rx' (0#1) [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/rtl/eth_axis_rx.v:34]
INFO: [Synth 8-6157] synthesizing module 'eth_axis_tx' [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/rtl/eth_axis_tx.v:34]
Parameter DATA_WIDTH bound to: 64 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'eth_axis_tx' (0#1) [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/rtl/eth_axis_tx.v:34]
INFO: [Synth 8-6157] synthesizing module 'udp_complete_64' [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/rtl/udp_complete_64.v:34]
INFO: [Synth 8-6157] synthesizing module 'ip_arb_mux' [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/rtl/ip_arb_mux.v:34]
Parameter S_COUNT bound to: 2 - type: integer
Parameter DATA_WIDTH bound to: 64 - type: integer
Parameter KEEP_ENABLE bound to: 1 - type: integer
Parameter ID_ENABLE bound to: 0 - type: integer
Parameter DEST_ENABLE bound to: 0 - type: integer
Parameter USER_ENABLE bound to: 1 - type: integer
Parameter USER_WIDTH bound to: 1 - type: integer
Parameter ARB_TYPE_ROUND_ROBIN bound to: 0 - type: integer
Parameter ARB_LSB_HIGH_PRIORITY bound to: 1 - type: integer
INFO: [Synth 8-6157] synthesizing module 'arbiter' [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/lib/axis/rtl/arbiter.v:34]
Parameter PORTS bound to: 2 - type: integer
Parameter ARB_TYPE_ROUND_ROBIN bound to: 0 - type: integer
Parameter ARB_BLOCK bound to: 1 - type: integer
Parameter ARB_BLOCK_ACK bound to: 1 - type: integer
Parameter ARB_LSB_HIGH_PRIORITY bound to: 1 - type: integer
INFO: [Synth 8-6157] synthesizing module 'priority_encoder' [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/lib/axis/rtl/priority_encoder.v:34]
Parameter WIDTH bound to: 2 - type: integer
Parameter LSB_HIGH_PRIORITY bound to: 1 - type: integer
WARNING: [Synth 8-693] zero replication count - replication ignored [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/lib/axis/rtl/priority_encoder.v:51]
INFO: [Synth 8-6155] done synthesizing module 'priority_encoder' (0#1) [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/lib/axis/rtl/priority_encoder.v:34]
INFO: [Synth 8-6155] done synthesizing module 'arbiter' (0#1) [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/lib/axis/rtl/arbiter.v:34]
INFO: [Synth 8-6155] done synthesizing module 'ip_arb_mux' (0#1) [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/rtl/ip_arb_mux.v:34]
INFO: [Synth 8-6157] synthesizing module 'ip_complete_64' [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/rtl/ip_complete_64.v:34]
Parameter ARP_CACHE_ADDR_WIDTH bound to: 9 - type: integer
Parameter ARP_REQUEST_RETRY_COUNT bound to: 4 - type: integer
Parameter ARP_REQUEST_RETRY_INTERVAL bound to: 250000000 - type: integer
Parameter ARP_REQUEST_TIMEOUT bound to: -544967296 - type: integer
INFO: [Synth 8-6157] synthesizing module 'eth_arb_mux' [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/rtl/eth_arb_mux.v:34]
Parameter S_COUNT bound to: 2 - type: integer
Parameter DATA_WIDTH bound to: 64 - type: integer
Parameter KEEP_ENABLE bound to: 1 - type: integer
Parameter ID_ENABLE bound to: 0 - type: integer
Parameter DEST_ENABLE bound to: 0 - type: integer
Parameter USER_ENABLE bound to: 1 - type: integer
Parameter USER_WIDTH bound to: 1 - type: integer
Parameter ARB_TYPE_ROUND_ROBIN bound to: 0 - type: integer
Parameter ARB_LSB_HIGH_PRIORITY bound to: 1 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'eth_arb_mux' (0#1) [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/rtl/eth_arb_mux.v:34]
INFO: [Synth 8-6157] synthesizing module 'ip_64' [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/rtl/ip_64.v:34]
INFO: [Synth 8-6157] synthesizing module 'ip_eth_rx_64' [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/rtl/ip_eth_rx_64.v:34]
INFO: [Synth 8-155] case statement is not full and has no default [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/rtl/ip_eth_rx_64.v:345]
INFO: [Synth 8-155] case statement is not full and has no default [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/rtl/ip_eth_rx_64.v:247]
INFO: [Synth 8-155] case statement is not full and has no default [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/rtl/ip_eth_rx_64.v:317]
INFO: [Synth 8-6155] done synthesizing module 'ip_eth_rx_64' (0#1) [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/rtl/ip_eth_rx_64.v:34]
INFO: [Synth 8-6157] synthesizing module 'ip_eth_tx_64' [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/rtl/ip_eth_tx_64.v:34]
INFO: [Synth 8-155] case statement is not full and has no default [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/rtl/ip_eth_tx_64.v:324]
INFO: [Synth 8-155] case statement is not full and has no default [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/rtl/ip_eth_tx_64.v:215]
INFO: [Synth 8-155] case statement is not full and has no default [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/rtl/ip_eth_tx_64.v:278]
INFO: [Synth 8-6155] done synthesizing module 'ip_eth_tx_64' (0#1) [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/rtl/ip_eth_tx_64.v:34]
INFO: [Synth 8-155] case statement is not full and has no default [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/rtl/ip_64.v:282]
INFO: [Synth 8-6155] done synthesizing module 'ip_64' (0#1) [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/rtl/ip_64.v:34]
INFO: [Synth 8-6157] synthesizing module 'arp' [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/rtl/arp.v:34]
Parameter DATA_WIDTH bound to: 64 - type: integer
Parameter KEEP_ENABLE bound to: 1 - type: integer
Parameter KEEP_WIDTH bound to: 8 - type: integer
Parameter CACHE_ADDR_WIDTH bound to: 9 - type: integer
Parameter REQUEST_RETRY_COUNT bound to: 4 - type: integer
Parameter REQUEST_RETRY_INTERVAL bound to: 250000000 - type: integer
Parameter REQUEST_TIMEOUT bound to: -544967296 - type: integer
INFO: [Synth 8-6157] synthesizing module 'arp_eth_rx' [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/rtl/arp_eth_rx.v:34]
Parameter DATA_WIDTH bound to: 64 - type: integer
Parameter KEEP_ENABLE bound to: 1 - type: integer
Parameter KEEP_WIDTH bound to: 8 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'arp_eth_rx' (0#1) [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/rtl/arp_eth_rx.v:34]
INFO: [Synth 8-6157] synthesizing module 'arp_eth_tx' [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/rtl/arp_eth_tx.v:34]
Parameter DATA_WIDTH bound to: 64 - type: integer
Parameter KEEP_ENABLE bound to: 1 - type: integer
Parameter KEEP_WIDTH bound to: 8 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'arp_eth_tx' (0#1) [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/rtl/arp_eth_tx.v:34]
INFO: [Synth 8-6157] synthesizing module 'arp_cache' [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/rtl/arp_cache.v:34]
Parameter CACHE_ADDR_WIDTH bound to: 9 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'arp_cache' (0#1) [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/rtl/arp_cache.v:34]
INFO: [Synth 8-6155] done synthesizing module 'arp' (0#1) [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/rtl/arp.v:34]
INFO: [Synth 8-6155] done synthesizing module 'ip_complete_64' (0#1) [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/rtl/ip_complete_64.v:34]
INFO: [Synth 8-6157] synthesizing module 'udp_64' [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/rtl/udp_64.v:34]
Parameter CHECKSUM_GEN_ENABLE bound to: 1 - type: integer
Parameter CHECKSUM_PAYLOAD_FIFO_DEPTH bound to: 2048 - type: integer
Parameter CHECKSUM_HEADER_FIFO_DEPTH bound to: 8 - type: integer
INFO: [Synth 8-6157] synthesizing module 'udp_checksum_gen_64' [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/rtl/udp_checksum_gen_64.v:34]
Parameter PAYLOAD_FIFO_DEPTH bound to: 2048 - type: integer
Parameter HEADER_FIFO_DEPTH bound to: 8 - type: integer
INFO: [Synth 8-6157] synthesizing module 'axis_fifo' [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/lib/axis/rtl/axis_fifo.v:34]
Parameter DEPTH bound to: 2048 - type: integer
Parameter DATA_WIDTH bound to: 64 - type: integer
Parameter KEEP_ENABLE bound to: 1 - type: integer
Parameter KEEP_WIDTH bound to: 8 - type: integer
Parameter LAST_ENABLE bound to: 1 - type: integer
Parameter ID_ENABLE bound to: 0 - type: integer
Parameter DEST_ENABLE bound to: 0 - type: integer
Parameter USER_ENABLE bound to: 1 - type: integer
Parameter USER_WIDTH bound to: 1 - type: integer
Parameter FRAME_FIFO bound to: 0 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'axis_fifo' (0#1) [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/lib/axis/rtl/axis_fifo.v:34]
INFO: [Synth 8-155] case statement is not full and has no default [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/rtl/udp_checksum_gen_64.v:462]
INFO: [Synth 8-6155] done synthesizing module 'udp_checksum_gen_64' (0#1) [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/rtl/udp_checksum_gen_64.v:34]
WARNING: [Synth 8-7071] port 'm_ip_protocol' of module 'udp_checksum_gen_64' is unconnected for instance 'udp_checksum_gen_64_inst' [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/rtl/udp_64.v:271]
WARNING: [Synth 8-7023] instance 'udp_checksum_gen_64_inst' of module 'udp_checksum_gen_64' has 55 connections declared, but only 54 given [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/rtl/udp_64.v:271]
INFO: [Synth 8-6157] synthesizing module 'udp_ip_rx_64' [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/rtl/udp_ip_rx_64.v:34]
INFO: [Synth 8-155] case statement is not full and has no default [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/rtl/udp_ip_rx_64.v:247]
INFO: [Synth 8-155] case statement is not full and has no default [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/rtl/udp_ip_rx_64.v:284]
INFO: [Synth 8-6155] done synthesizing module 'udp_ip_rx_64' (0#1) [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/rtl/udp_ip_rx_64.v:34]
INFO: [Synth 8-6157] synthesizing module 'udp_ip_tx_64' [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/rtl/udp_ip_tx_64.v:34]
INFO: [Synth 8-155] case statement is not full and has no default [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/rtl/udp_ip_tx_64.v:238]
INFO: [Synth 8-155] case statement is not full and has no default [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/rtl/udp_ip_tx_64.v:273]
INFO: [Synth 8-6155] done synthesizing module 'udp_ip_tx_64' (0#1) [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/rtl/udp_ip_tx_64.v:34]
INFO: [Synth 8-6155] done synthesizing module 'udp_64' (0#1) [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/rtl/udp_64.v:34]
INFO: [Synth 8-6155] done synthesizing module 'udp_complete_64' (0#1) [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/rtl/udp_complete_64.v:34]
INFO: [Synth 8-6157] synthesizing module 'axis_fifo__parameterized0' [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/lib/axis/rtl/axis_fifo.v:34]
Parameter DEPTH bound to: 8192 - type: integer
Parameter DATA_WIDTH bound to: 64 - type: integer
Parameter KEEP_ENABLE bound to: 1 - type: integer
Parameter KEEP_WIDTH bound to: 8 - type: integer
Parameter ID_ENABLE bound to: 0 - type: integer
Parameter DEST_ENABLE bound to: 0 - type: integer
Parameter USER_ENABLE bound to: 1 - type: integer
Parameter USER_WIDTH bound to: 1 - type: integer
Parameter FRAME_FIFO bound to: 0 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'axis_fifo__parameterized0' (0#1) [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/lib/axis/rtl/axis_fifo.v:34]
INFO: [Synth 8-6155] done synthesizing module 'fpga_core' (0#1) [/home/victor/verilog-ethernet/example/KR260/fpga/rtl/fpga_core.v:35]
INFO: [Synth 8-6155] done synthesizing module 'fpga' (0#1) [/home/victor/verilog-ethernet/example/KR260/fpga/rtl/fpga.v:35]
WARNING: [Synth 8-3848] Net xcvr_qpll0reset_out in module/entity eth_xcvr_phy_wrapper does not have driver. [/home/victor/verilog-ethernet/example/KR260/fpga/rtl/eth_xcvr_phy_wrapper.v:68]
WARNING: [Synth 8-6014] Unused sequential element ptp_ts_reg_reg was removed. [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/rtl/axis_xgmii_rx_64.v:428]
WARNING: [Synth 8-6014] Unused sequential element m_axis_ptp_ts_reg_reg was removed. [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/rtl/axis_xgmii_tx_64.v:603]
WARNING: [Synth 8-6014] Unused sequential element m_axis_ptp_ts_adj_reg_reg was removed. [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/rtl/axis_xgmii_tx_64.v:604]
WARNING: [Synth 8-6014] Unused sequential element m_axis_ptp_ts_tag_reg_reg was removed. [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/rtl/axis_xgmii_tx_64.v:605]
WARNING: [Synth 8-6014] Unused sequential element m_axis_ptp_ts_valid_reg_reg was removed. [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/rtl/axis_xgmii_tx_64.v:606]
WARNING: [Synth 8-6014] Unused sequential element m_axis_ptp_ts_valid_int_reg_reg was removed. [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/rtl/axis_xgmii_tx_64.v:607]
WARNING: [Synth 8-6014] Unused sequential element m_axis_ptp_ts_borrow_reg_reg was removed. [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/rtl/axis_xgmii_tx_64.v:608]
WARNING: [Synth 8-6014] Unused sequential element wr_ptr_temp_reg was removed. [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/lib/axis/rtl/axis_async_fifo.v:373]
WARNING: [Synth 8-6014] Unused sequential element send_frame_reg_reg was removed. [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/lib/axis/rtl/axis_async_fifo.v:386]
WARNING: [Synth 8-6014] Unused sequential element wr_ptr_gray_sync2_reg_reg was removed. [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/lib/axis/rtl/axis_async_fifo.v:484]
WARNING: [Synth 8-6014] Unused sequential element rd_ptr_temp_reg was removed. [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/lib/axis/rtl/axis_async_fifo.v:565]
WARNING: [Synth 8-6014] Unused sequential element wr_ptr_temp_reg was removed. [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/lib/axis/rtl/axis_async_fifo.v:373]
WARNING: [Synth 8-6014] Unused sequential element send_frame_reg_reg was removed. [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/lib/axis/rtl/axis_async_fifo.v:386]
WARNING: [Synth 8-6014] Unused sequential element wr_ptr_gray_sync2_reg_reg was removed. [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/lib/axis/rtl/axis_async_fifo.v:484]
WARNING: [Synth 8-6014] Unused sequential element rd_ptr_temp_reg was removed. [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/lib/axis/rtl/axis_async_fifo.v:565]
WARNING: [Synth 8-6014] Unused sequential element m_ip_payload_axis_tid_reg_reg was removed. [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/rtl/ip_arb_mux.v:376]
WARNING: [Synth 8-6014] Unused sequential element m_ip_payload_axis_tdest_reg_reg was removed. [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/rtl/ip_arb_mux.v:377]
WARNING: [Synth 8-6014] Unused sequential element temp_m_ip_payload_axis_tid_reg_reg was removed. [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/rtl/ip_arb_mux.v:383]
WARNING: [Synth 8-6014] Unused sequential element temp_m_ip_payload_axis_tdest_reg_reg was removed. [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/rtl/ip_arb_mux.v:384]
WARNING: [Synth 8-6014] Unused sequential element m_eth_payload_axis_tid_reg_reg was removed. [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/rtl/eth_arb_mux.v:285]
WARNING: [Synth 8-6014] Unused sequential element m_eth_payload_axis_tdest_reg_reg was removed. [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/rtl/eth_arb_mux.v:286]
WARNING: [Synth 8-6014] Unused sequential element temp_m_eth_payload_axis_tid_reg_reg was removed. [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/rtl/eth_arb_mux.v:292]
WARNING: [Synth 8-6014] Unused sequential element temp_m_eth_payload_axis_tdest_reg_reg was removed. [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/rtl/eth_arb_mux.v:293]
WARNING: [Synth 8-6014] Unused sequential element busy_reg_reg was removed. [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/rtl/arp_eth_rx.v:172]
WARNING: [Synth 8-6014] Unused sequential element busy_reg_reg was removed. [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/rtl/arp_eth_tx.v:161]
WARNING: [Synth 8-6014] Unused sequential element wr_ptr_cur_reg_reg was removed. [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/lib/axis/rtl/axis_fifo.v:174]
WARNING: [Synth 8-6014] Unused sequential element drop_frame_reg_reg was removed. [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/lib/axis/rtl/axis_fifo.v:267]
WARNING: [Synth 8-6014] Unused sequential element send_frame_reg_reg was removed. [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/lib/axis/rtl/axis_fifo.v:268]
WARNING: [Synth 8-6014] Unused sequential element bad_frame_reg_reg was removed. [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/lib/axis/rtl/axis_fifo.v:213]
WARNING: [Synth 8-6014] Unused sequential element good_frame_reg_reg was removed. [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/lib/axis/rtl/axis_fifo.v:214]
WARNING: [Synth 8-6014] Unused sequential element s_udp_payload_axis_tready_reg_reg was removed. [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/rtl/udp_checksum_gen_64.v:555]
WARNING: [Synth 8-6014] Unused sequential element wr_ptr_cur_reg_reg was removed. [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/lib/axis/rtl/axis_fifo.v:174]
WARNING: [Synth 8-6014] Unused sequential element drop_frame_reg_reg was removed. [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/lib/axis/rtl/axis_fifo.v:267]
WARNING: [Synth 8-6014] Unused sequential element send_frame_reg_reg was removed. [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/lib/axis/rtl/axis_fifo.v:268]
WARNING: [Synth 8-6014] Unused sequential element bad_frame_reg_reg was removed. [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/lib/axis/rtl/axis_fifo.v:213]
WARNING: [Synth 8-6014] Unused sequential element good_frame_reg_reg was removed. [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/lib/axis/rtl/axis_fifo.v:214]
WARNING: [Synth 8-3917] design fpga has port sfp0_tx_disable_b driven by constant 1
WARNING: [Synth 8-7129] Port s_axis_tid[7] in module axis_fifo__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axis_tid[6] in module axis_fifo__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axis_tid[5] in module axis_fifo__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axis_tid[4] in module axis_fifo__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axis_tid[3] in module axis_fifo__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axis_tid[2] in module axis_fifo__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axis_tid[1] in module axis_fifo__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axis_tid[0] in module axis_fifo__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axis_tdest[7] in module axis_fifo__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axis_tdest[6] in module axis_fifo__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axis_tdest[5] in module axis_fifo__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axis_tdest[4] in module axis_fifo__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axis_tdest[3] in module axis_fifo__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axis_tdest[2] in module axis_fifo__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axis_tdest[1] in module axis_fifo__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axis_tdest[0] in module axis_fifo__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axis_tid[7] in module axis_fifo is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axis_tid[6] in module axis_fifo is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axis_tid[5] in module axis_fifo is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axis_tid[4] in module axis_fifo is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axis_tid[3] in module axis_fifo is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axis_tid[2] in module axis_fifo is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axis_tid[1] in module axis_fifo is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axis_tid[0] in module axis_fifo is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axis_tdest[7] in module axis_fifo is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axis_tdest[6] in module axis_fifo is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axis_tdest[5] in module axis_fifo is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axis_tdest[4] in module axis_fifo is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axis_tdest[3] in module axis_fifo is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axis_tdest[2] in module axis_fifo is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axis_tdest[1] in module axis_fifo is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axis_tdest[0] in module axis_fifo is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_udp_length[15] in module udp_64 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_udp_length[14] in module udp_64 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_udp_length[13] in module udp_64 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_udp_length[12] in module udp_64 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_udp_length[11] in module udp_64 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_udp_length[10] in module udp_64 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_udp_length[9] in module udp_64 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_udp_length[8] in module udp_64 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_udp_length[7] in module udp_64 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_udp_length[6] in module udp_64 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_udp_length[5] in module udp_64 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_udp_length[4] in module udp_64 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_udp_length[3] in module udp_64 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_udp_length[2] in module udp_64 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_udp_length[1] in module udp_64 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_udp_length[0] in module udp_64 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_udp_checksum[15] in module udp_64 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_udp_checksum[14] in module udp_64 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_udp_checksum[13] in module udp_64 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_udp_checksum[12] in module udp_64 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_udp_checksum[11] in module udp_64 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_udp_checksum[10] in module udp_64 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_udp_checksum[9] in module udp_64 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_udp_checksum[8] in module udp_64 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_udp_checksum[7] in module udp_64 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_udp_checksum[6] in module udp_64 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_udp_checksum[5] in module udp_64 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_udp_checksum[4] in module udp_64 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_udp_checksum[3] in module udp_64 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_udp_checksum[2] in module udp_64 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_udp_checksum[1] in module udp_64 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_udp_checksum[0] in module udp_64 is either unconnected or has no load
WARNING: [Synth 8-7129] Port local_ip[31] in module ip_64 is either unconnected or has no load
WARNING: [Synth 8-7129] Port local_ip[30] in module ip_64 is either unconnected or has no load
WARNING: [Synth 8-7129] Port local_ip[29] in module ip_64 is either unconnected or has no load
WARNING: [Synth 8-7129] Port local_ip[28] in module ip_64 is either unconnected or has no load
WARNING: [Synth 8-7129] Port local_ip[27] in module ip_64 is either unconnected or has no load
WARNING: [Synth 8-7129] Port local_ip[26] in module ip_64 is either unconnected or has no load
WARNING: [Synth 8-7129] Port local_ip[25] in module ip_64 is either unconnected or has no load
WARNING: [Synth 8-7129] Port local_ip[24] in module ip_64 is either unconnected or has no load
WARNING: [Synth 8-7129] Port local_ip[23] in module ip_64 is either unconnected or has no load
WARNING: [Synth 8-7129] Port local_ip[22] in module ip_64 is either unconnected or has no load
WARNING: [Synth 8-7129] Port local_ip[21] in module ip_64 is either unconnected or has no load
WARNING: [Synth 8-7129] Port local_ip[20] in module ip_64 is either unconnected or has no load
WARNING: [Synth 8-7129] Port local_ip[19] in module ip_64 is either unconnected or has no load
WARNING: [Synth 8-7129] Port local_ip[18] in module ip_64 is either unconnected or has no load
WARNING: [Synth 8-7129] Port local_ip[17] in module ip_64 is either unconnected or has no load
WARNING: [Synth 8-7129] Port local_ip[16] in module ip_64 is either unconnected or has no load
WARNING: [Synth 8-7129] Port local_ip[15] in module ip_64 is either unconnected or has no load
WARNING: [Synth 8-7129] Port local_ip[14] in module ip_64 is either unconnected or has no load
WARNING: [Synth 8-7129] Port local_ip[13] in module ip_64 is either unconnected or has no load
WARNING: [Synth 8-7129] Port local_ip[12] in module ip_64 is either unconnected or has no load
WARNING: [Synth 8-7129] Port local_ip[11] in module ip_64 is either unconnected or has no load
WARNING: [Synth 8-7129] Port local_ip[10] in module ip_64 is either unconnected or has no load
WARNING: [Synth 8-7129] Port local_ip[9] in module ip_64 is either unconnected or has no load
WARNING: [Synth 8-7129] Port local_ip[8] in module ip_64 is either unconnected or has no load
WARNING: [Synth 8-7129] Port local_ip[7] in module ip_64 is either unconnected or has no load
WARNING: [Synth 8-7129] Port local_ip[6] in module ip_64 is either unconnected or has no load
WARNING: [Synth 8-7129] Port local_ip[5] in module ip_64 is either unconnected or has no load
WARNING: [Synth 8-7129] Port local_ip[4] in module ip_64 is either unconnected or has no load
WARNING: [Synth 8-7129] Port local_ip[3] in module ip_64 is either unconnected or has no load
WARNING: [Synth 8-7129] Port local_ip[2] in module ip_64 is either unconnected or has no load
WARNING: [Synth 8-7129] Port local_ip[1] in module ip_64 is either unconnected or has no load
WARNING: [Synth 8-7129] Port local_ip[0] in module ip_64 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_eth_payload_axis_tid[15] in module eth_arb_mux is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_eth_payload_axis_tid[14] in module eth_arb_mux is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_eth_payload_axis_tid[13] in module eth_arb_mux is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_eth_payload_axis_tid[12] in module eth_arb_mux is either unconnected or has no load
INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:05:21 ; elapsed = 00:05:23 . Memory (MB): peak = 6201.648 ; gain = 3487.969 ; free physical = 42780 ; free virtual = 60657
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:05:22 ; elapsed = 00:05:24 . Memory (MB): peak = 6201.648 ; gain = 3487.969 ; free physical = 42780 ; free virtual = 60657
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:05:22 ; elapsed = 00:05:24 . Memory (MB): peak = 6201.648 ; gain = 3487.969 ; free physical = 42780 ; free virtual = 60657
---------------------------------------------------------------------------------
Netlist sorting complete. Time (s): cpu = 00:00:00.14 ; elapsed = 00:00:00.14 . Memory (MB): peak = 6201.648 ; gain = 0.000 ; free physical = 42774 ; free virtual = 60651
INFO: [Netlist 29-17] Analyzing 4 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-570] Preparing netlist for logic optimization
Processing XDC Constraints
Initializing timing engine
Parsing XDC File [/home/victor/verilog-ethernet/example/KR260/fpga/fpga/fpga.gen/sources_1/ip/eth_xcvr_gt_full/eth_xcvr_gt_full/eth_xcvr_gt_full_in_context.xdc] for cell 'sfp0_phy_inst/xcvr.eth_xcvr_gt_full_inst'
Finished Parsing XDC File [/home/victor/verilog-ethernet/example/KR260/fpga/fpga/fpga.gen/sources_1/ip/eth_xcvr_gt_full/eth_xcvr_gt_full/eth_xcvr_gt_full_in_context.xdc] for cell 'sfp0_phy_inst/xcvr.eth_xcvr_gt_full_inst'
Parsing XDC File [/home/victor/verilog-ethernet/example/KR260/fpga/fpga.xdc]
INFO: [Constraints 18-632] set_output_delay: No clock object specified, the clocks will be automatically identified [/home/victor/verilog-ethernet/example/KR260/fpga/fpga.xdc:48]
INFO: [Constraints 18-632] set_input_delay: No clock object specified, the clocks will be automatically identified [/home/victor/verilog-ethernet/example/KR260/fpga/fpga.xdc:58]
INFO: [Constraints 18-632] set_output_delay: No clock object specified, the clocks will be automatically identified [/home/victor/verilog-ethernet/example/KR260/fpga/fpga.xdc:124]
Finished Parsing XDC File [/home/victor/verilog-ethernet/example/KR260/fpga/fpga.xdc]
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/victor/verilog-ethernet/example/KR260/fpga/fpga.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/fpga_propImpl.xdc].
Resolution: To avoid this warning, move constraints listed in [.Xil/fpga_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
Sourcing Tcl File [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/syn/vivado/eth_mac_fifo.tcl]
Inserting timing constraints for ethernet MAC with FIFO instance core_inst/eth_mac_10g_fifo_inst
INFO: [Timing 38-2] Deriving generated clocks [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/syn/vivado/eth_mac_fifo.tcl:23]
Finished Sourcing Tcl File [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/syn/vivado/eth_mac_fifo.tcl]
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/syn/vivado/eth_mac_fifo.tcl]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/fpga_propImpl.xdc].
Resolution: To avoid this warning, move constraints listed in [.Xil/fpga_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
Sourcing Tcl File [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl]
Inserting timing constraints for axis_async_fifo instance core_inst/eth_mac_10g_fifo_inst/rx_fifo/fifo_inst
Inserting timing constraints for axis_async_fifo instance core_inst/eth_mac_10g_fifo_inst/tx_fifo/fifo_inst
Finished Sourcing Tcl File [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl]
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/fpga_propImpl.xdc].
Resolution: To avoid this warning, move constraints listed in [.Xil/fpga_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
Sourcing Tcl File [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/lib/axis/syn/vivado/sync_reset.tcl]
Inserting timing constraints for sync_reset instance sync_reset_125mhz_inst
Inserting timing constraints for sync_reset instance sfp0_phy_inst/rx_reset_sync_inst
Inserting timing constraints for sync_reset instance sfp0_phy_inst/tx_reset_sync_inst
Finished Sourcing Tcl File [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/lib/axis/syn/vivado/sync_reset.tcl]
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/lib/axis/syn/vivado/sync_reset.tcl]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/fpga_propImpl.xdc].
Resolution: To avoid this warning, move constraints listed in [.Xil/fpga_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
Completed Processing XDC Constraints
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 6320.484 ; gain = 0.000 ; free physical = 42724 ; free virtual = 60601
INFO: [Project 1-111] Unisim Transformation Summary:
A total of 4 instances were transformed.
BUFG => BUFGCE: 2 instances
IBUFGDS => IBUFDS (DIFFINBUF, IBUFCTRL): 1 instance
MMCME4_BASE => MMCME4_ADV: 1 instance
Constraint Validation Runtime : Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.05 . Memory (MB): peak = 6320.484 ; gain = 0.000 ; free physical = 42724 ; free virtual = 60601
WARNING: [Timing 38-316] Clock period '8.000' specified during out-of-context synthesis of instance 'sfp0_phy_inst/xcvr.eth_xcvr_gt_full_inst' at clock pin 'gtwiz_reset_clk_freerun_in[0]' is different from the actual clock period '6.400', this can lead to different synthesis results.
INFO: [Designutils 20-5440] No compile time benefit to using incremental synthesis; A full resynthesis will be run
INFO: [Designutils 20-4379] Flow is switching to default flow due to incremental criteria not met. If you would like to alter this behaviour and have the flow terminate instead, please set the following parameter config_implementation {autoIncr.Synth.RejectBehavior Terminate}
---------------------------------------------------------------------------------
Finished Constraint Validation : Time (s): cpu = 00:05:34 ; elapsed = 00:05:36 . Memory (MB): peak = 6320.484 ; gain = 3606.805 ; free physical = 43169 ; free virtual = 61046
---------------------------------------------------------------------------------
INFO: [Synth 8-6904] The RAM "udp_checksum_gen_64:/eth_dest_mac_mem_reg" of size (depth=8 x width=48) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "udp_checksum_gen_64:/eth_src_mac_mem_reg" of size (depth=8 x width=48) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "udp_checksum_gen_64:/eth_type_mem_reg" of size (depth=8 x width=16) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "udp_checksum_gen_64:/ip_version_mem_reg" of size (depth=8 x width=4) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "udp_checksum_gen_64:/ip_ihl_mem_reg" of size (depth=8 x width=4) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "udp_checksum_gen_64:/ip_dscp_mem_reg" of size (depth=8 x width=6) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "udp_checksum_gen_64:/ip_ecn_mem_reg" of size (depth=8 x width=2) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "udp_checksum_gen_64:/udp_length_mem_reg" of size (depth=8 x width=16) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "udp_checksum_gen_64:/ip_identification_mem_reg" of size (depth=8 x width=16) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "udp_checksum_gen_64:/ip_flags_mem_reg" of size (depth=8 x width=3) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "udp_checksum_gen_64:/ip_fragment_offset_mem_reg" of size (depth=8 x width=13) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "udp_checksum_gen_64:/ip_ttl_mem_reg" of size (depth=8 x width=8) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "udp_checksum_gen_64:/ip_header_checksum_mem_reg" of size (depth=8 x width=16) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "udp_checksum_gen_64:/ip_source_ip_mem_reg" of size (depth=8 x width=32) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "udp_checksum_gen_64:/ip_dest_ip_mem_reg" of size (depth=8 x width=32) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "udp_checksum_gen_64:/udp_source_port_mem_reg" of size (depth=8 x width=16) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "udp_checksum_gen_64:/udp_dest_port_mem_reg" of size (depth=8 x width=16) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "udp_checksum_gen_64:/udp_checksum_mem_reg" of size (depth=8 x width=16) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
STATE_IDLE | 0001 | 000
STATE_READ_HEADER | 0010 | 001
STATE_READ_PAYLOAD | 0100 | 010
STATE_READ_PAYLOAD_LAST | 1000 | 011
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'state_reg_reg' using encoding 'one-hot' in module 'udp_ip_rx_64'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
STATE_IDLE | 00 | 000
STATE_WRITE_HEADER | 01 | 001
STATE_WRITE_PAYLOAD | 10 | 010
STATE_WRITE_PAYLOAD_LAST | 11 | 011
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'state_reg_reg' using encoding 'sequential' in module 'udp_ip_tx_64'
INFO: [Synth 8-7030] Implemented Non-Cascaded Block Ram (cascade_height = 1) of width 36 for RAM "axis_fifo__parameterized0:/mem_reg"
INFO: [Synth 8-7030] Implemented Non-Cascaded Block Ram (cascade_height = 1) of width 36 for RAM "axis_fifo__parameterized0:/mem_reg"
INFO: [Synth 8-7030] Implemented Non-Cascaded Block Ram (cascade_height = 1) of width 2 for RAM "axis_fifo__parameterized0:/mem_reg"
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:05:41 ; elapsed = 00:05:44 . Memory (MB): peak = 6320.484 ; gain = 3606.805 ; free physical = 41298 ; free virtual = 59179
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start RTL Component Statistics
---------------------------------------------------------------------------------
Detailed RTL Component Info :
+---Adders :
2 Input 36 Bit Adders := 1
2 Input 32 Bit Adders := 2
3 Input 32 Bit Adders := 1
3 Input 20 Bit Adders := 1
9 Input 20 Bit Adders := 1
3 Input 18 Bit Adders := 1
2 Input 18 Bit Adders := 1
2 Input 17 Bit Adders := 7
4 Input 17 Bit Adders := 2
2 Input 16 Bit Adders := 12
2 Input 15 Bit Adders := 2
2 Input 11 Bit Adders := 3
2 Input 10 Bit Adders := 7
2 Input 9 Bit Adders := 4
2 Input 8 Bit Adders := 1
5 Input 8 Bit Adders := 1
2 Input 6 Bit Adders := 5
2 Input 4 Bit Adders := 6
2 Input 3 Bit Adders := 2
2 Input 2 Bit Adders := 2
2 Input 1 Bit Adders := 2
+---XORs :
2 Input 32 Bit XORs := 1
2 Input 11 Bit XORs := 1
2 Input 10 Bit XORs := 10
2 Input 9 Bit XORs := 1
2 Input 2 Bit XORs := 1
3 Input 1 Bit XORs := 301
2 Input 1 Bit XORs := 797
4 Input 1 Bit XORs := 91
5 Input 1 Bit XORs := 52
6 Input 1 Bit XORs := 66
7 Input 1 Bit XORs := 47
10 Input 1 Bit XORs := 26
9 Input 1 Bit XORs := 33
8 Input 1 Bit XORs := 44
11 Input 1 Bit XORs := 25
12 Input 1 Bit XORs := 23
17 Input 1 Bit XORs := 39
18 Input 1 Bit XORs := 33
16 Input 1 Bit XORs := 34
20 Input 1 Bit XORs := 29
19 Input 1 Bit XORs := 25
21 Input 1 Bit XORs := 21
15 Input 1 Bit XORs := 31
24 Input 1 Bit XORs := 24
26 Input 1 Bit XORs := 16
25 Input 1 Bit XORs := 12
22 Input 1 Bit XORs := 26
27 Input 1 Bit XORs := 12
28 Input 1 Bit XORs := 14
29 Input 1 Bit XORs := 4
35 Input 1 Bit XORs := 4
30 Input 1 Bit XORs := 3
34 Input 1 Bit XORs := 2
33 Input 1 Bit XORs := 2
23 Input 1 Bit XORs := 11
32 Input 1 Bit XORs := 7
31 Input 1 Bit XORs := 4
43 Input 1 Bit XORs := 2
37 Input 1 Bit XORs := 2
13 Input 1 Bit XORs := 11
14 Input 1 Bit XORs := 13
+---Registers :
74 Bit Registers := 8
64 Bit Registers := 35
58 Bit Registers := 2
48 Bit Registers := 32
36 Bit Registers := 1
32 Bit Registers := 24
20 Bit Registers := 2
17 Bit Registers := 4
16 Bit Registers := 50
15 Bit Registers := 2
13 Bit Registers := 6
11 Bit Registers := 2
10 Bit Registers := 19
9 Bit Registers := 4
8 Bit Registers := 48
6 Bit Registers := 11
4 Bit Registers := 23
3 Bit Registers := 9
2 Bit Registers := 27
1 Bit Registers := 257
+---RAMs :
74K Bit (1024 X 74 bit) RAMs := 1
37K Bit (512 X 74 bit) RAMs := 2
24K Bit (512 X 48 bit) RAMs := 1
18K Bit (256 X 74 bit) RAMs := 1
16K Bit (512 X 32 bit) RAMs := 1
512 Bit (512 X 1 bit) RAMs := 1
384 Bit (8 X 48 bit) RAMs := 2
256 Bit (8 X 32 bit) RAMs := 2
128 Bit (8 X 16 bit) RAMs := 7
104 Bit (8 X 13 bit) RAMs := 1
64 Bit (8 X 8 bit) RAMs := 1
48 Bit (8 X 6 bit) RAMs := 1
32 Bit (8 X 4 bit) RAMs := 2
24 Bit (8 X 3 bit) RAMs := 1
16 Bit (8 X 2 bit) RAMs := 1
+---Muxes :
16 Input 64 Bit Muxes := 1
3 Input 64 Bit Muxes := 3
2 Input 64 Bit Muxes := 46
7 Input 64 Bit Muxes := 2
5 Input 64 Bit Muxes := 1
6 Input 64 Bit Muxes := 1
4 Input 64 Bit Muxes := 2
2 Input 48 Bit Muxes := 21
6 Input 36 Bit Muxes := 1
3 Input 36 Bit Muxes := 1
2 Input 36 Bit Muxes := 1
2 Input 32 Bit Muxes := 15
8 Input 32 Bit Muxes := 1
6 Input 32 Bit Muxes := 1
5 Input 28 Bit Muxes := 1
5 Input 20 Bit Muxes := 1
6 Input 17 Bit Muxes := 2
2 Input 16 Bit Muxes := 15
5 Input 16 Bit Muxes := 1
6 Input 16 Bit Muxes := 2
4 Input 16 Bit Muxes := 2
2 Input 15 Bit Muxes := 1
2 Input 13 Bit Muxes := 1
2 Input 10 Bit Muxes := 24
2 Input 9 Bit Muxes := 1
10 Input 8 Bit Muxes := 8
2 Input 8 Bit Muxes := 81
16 Input 8 Bit Muxes := 1
9 Input 8 Bit Muxes := 2
3 Input 8 Bit Muxes := 7
8 Input 8 Bit Muxes := 2
7 Input 8 Bit Muxes := 2
5 Input 8 Bit Muxes := 5
4 Input 8 Bit Muxes := 7
6 Input 8 Bit Muxes := 1
11 Input 8 Bit Muxes := 1
11 Input 7 Bit Muxes := 8
2 Input 6 Bit Muxes := 5
7 Input 6 Bit Muxes := 1
5 Input 6 Bit Muxes := 1
6 Input 6 Bit Muxes := 2
4 Input 4 Bit Muxes := 2
2 Input 4 Bit Muxes := 17
16 Input 4 Bit Muxes := 1
8 Input 4 Bit Muxes := 1
9 Input 4 Bit Muxes := 5
3 Input 4 Bit Muxes := 1
2 Input 3 Bit Muxes := 31
9 Input 3 Bit Muxes := 1
7 Input 3 Bit Muxes := 1
21 Input 3 Bit Muxes := 1
4 Input 3 Bit Muxes := 3
3 Input 3 Bit Muxes := 9
5 Input 3 Bit Muxes := 1
28 Input 3 Bit Muxes := 1
6 Input 3 Bit Muxes := 4
3 Input 2 Bit Muxes := 9
2 Input 2 Bit Muxes := 58
7 Input 2 Bit Muxes := 1
4 Input 2 Bit Muxes := 2
2 Input 1 Bit Muxes := 393
4 Input 1 Bit Muxes := 30
10 Input 1 Bit Muxes := 8
16 Input 1 Bit Muxes := 2
18 Input 1 Bit Muxes := 1
11 Input 1 Bit Muxes := 8
3 Input 1 Bit Muxes := 16
7 Input 1 Bit Muxes := 10
5 Input 1 Bit Muxes := 22
6 Input 1 Bit Muxes := 20
---------------------------------------------------------------------------------
Finished RTL Component Statistics
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Part Resource Summary
---------------------------------------------------------------------------------
Part Resources:
DSPs: 2520 (col length:168)
BRAMs: 1824 (col length: RAMB18 168 RAMB36 84)
---------------------------------------------------------------------------------
Finished Part Resource Summary
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Cross Boundary and Area Optimization
---------------------------------------------------------------------------------
WARNING: [Synth 8-7080] Parallel synthesis criteria is not met
INFO: [Synth 8-6904] The RAM "core_inst/udp_complete_inst/\ip_complete_64_inst/arp_inst /arp_cache_inst/valid_mem_reg" of size (depth=512 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "core_inst/udp_complete_inst/udp_64_inst/udp_checksum_gen_64_inst/eth_dest_mac_mem_reg" of size (depth=8 x width=48) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "core_inst/udp_complete_inst/udp_64_inst/udp_checksum_gen_64_inst/eth_src_mac_mem_reg" of size (depth=8 x width=48) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "core_inst/udp_complete_inst/udp_64_inst/udp_checksum_gen_64_inst/eth_type_mem_reg" of size (depth=8 x width=16) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "core_inst/udp_complete_inst/udp_64_inst/udp_checksum_gen_64_inst/ip_version_mem_reg" of size (depth=8 x width=4) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "core_inst/udp_complete_inst/udp_64_inst/udp_checksum_gen_64_inst/ip_ihl_mem_reg" of size (depth=8 x width=4) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "core_inst/udp_complete_inst/udp_64_inst/udp_checksum_gen_64_inst/ip_dscp_mem_reg" of size (depth=8 x width=6) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "core_inst/udp_complete_inst/udp_64_inst/udp_checksum_gen_64_inst/ip_ecn_mem_reg" of size (depth=8 x width=2) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "core_inst/udp_complete_inst/udp_64_inst/udp_checksum_gen_64_inst/udp_length_mem_reg" of size (depth=8 x width=16) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "core_inst/udp_complete_inst/udp_64_inst/udp_checksum_gen_64_inst/ip_identification_mem_reg" of size (depth=8 x width=16) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "core_inst/udp_complete_inst/udp_64_inst/udp_checksum_gen_64_inst/ip_flags_mem_reg" of size (depth=8 x width=3) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "core_inst/udp_complete_inst/udp_64_inst/udp_checksum_gen_64_inst/ip_fragment_offset_mem_reg" of size (depth=8 x width=13) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "core_inst/udp_complete_inst/udp_64_inst/udp_checksum_gen_64_inst/ip_ttl_mem_reg" of size (depth=8 x width=8) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "core_inst/udp_complete_inst/udp_64_inst/udp_checksum_gen_64_inst/ip_header_checksum_mem_reg" of size (depth=8 x width=16) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "core_inst/udp_complete_inst/udp_64_inst/udp_checksum_gen_64_inst/ip_source_ip_mem_reg" of size (depth=8 x width=32) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "core_inst/udp_complete_inst/udp_64_inst/udp_checksum_gen_64_inst/ip_dest_ip_mem_reg" of size (depth=8 x width=32) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "core_inst/udp_complete_inst/udp_64_inst/udp_checksum_gen_64_inst/udp_source_port_mem_reg" of size (depth=8 x width=16) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "core_inst/udp_complete_inst/udp_64_inst/udp_checksum_gen_64_inst/udp_dest_port_mem_reg" of size (depth=8 x width=16) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "core_inst/udp_complete_inst/udp_64_inst/udp_checksum_gen_64_inst/udp_checksum_mem_reg" of size (depth=8 x width=16) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
WARNING: [Synth 8-3917] design fpga has port sfp0_tx_disable_b driven by constant 1
RAM Pipeline Warning: Read Address Register Found For RAM ip_addr_mem_reg. We will not be able to pipeline it. This may degrade performance.
RAM Pipeline Warning: Read Address Register Found For RAM ip_addr_mem_reg. We will not be able to pipeline it. This may degrade performance.
RAM Pipeline Warning: Read Address Register Found For RAM valid_mem_reg. We will not be able to pipeline it. This may degrade performance.
RAM Pipeline Warning: Read Address Register Found For RAM valid_mem_reg. We will not be able to pipeline it. This may degrade performance.
INFO: [Synth 8-6904] The RAM "core_inst/udp_complete_inst/\ip_complete_64_inst/arp_inst /arp_cache_inst/valid_mem_reg" of size (depth=512 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "core_inst/udp_complete_inst/udp_64_inst/udp_checksum_gen_64_inst/eth_dest_mac_mem_reg" of size (depth=8 x width=48) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "core_inst/udp_complete_inst/udp_64_inst/udp_checksum_gen_64_inst/eth_src_mac_mem_reg" of size (depth=8 x width=48) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "core_inst/udp_complete_inst/udp_64_inst/udp_checksum_gen_64_inst/eth_type_mem_reg" of size (depth=8 x width=16) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "core_inst/udp_complete_inst/udp_64_inst/udp_checksum_gen_64_inst/ip_version_mem_reg" of size (depth=8 x width=4) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "core_inst/udp_complete_inst/udp_64_inst/udp_checksum_gen_64_inst/ip_ihl_mem_reg" of size (depth=8 x width=4) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "core_inst/udp_complete_inst/udp_64_inst/udp_checksum_gen_64_inst/ip_dscp_mem_reg" of size (depth=8 x width=6) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "core_inst/udp_complete_inst/udp_64_inst/udp_checksum_gen_64_inst/ip_ecn_mem_reg" of size (depth=8 x width=2) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "core_inst/udp_complete_inst/udp_64_inst/udp_checksum_gen_64_inst/udp_length_mem_reg" of size (depth=8 x width=16) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "core_inst/udp_complete_inst/udp_64_inst/udp_checksum_gen_64_inst/ip_identification_mem_reg" of size (depth=8 x width=16) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "core_inst/udp_complete_inst/udp_64_inst/udp_checksum_gen_64_inst/ip_flags_mem_reg" of size (depth=8 x width=3) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "core_inst/udp_complete_inst/udp_64_inst/udp_checksum_gen_64_inst/ip_fragment_offset_mem_reg" of size (depth=8 x width=13) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "core_inst/udp_complete_inst/udp_64_inst/udp_checksum_gen_64_inst/ip_ttl_mem_reg" of size (depth=8 x width=8) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "core_inst/udp_complete_inst/udp_64_inst/udp_checksum_gen_64_inst/ip_header_checksum_mem_reg" of size (depth=8 x width=16) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "core_inst/udp_complete_inst/udp_64_inst/udp_checksum_gen_64_inst/ip_source_ip_mem_reg" of size (depth=8 x width=32) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "core_inst/udp_complete_inst/udp_64_inst/udp_checksum_gen_64_inst/ip_dest_ip_mem_reg" of size (depth=8 x width=32) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "core_inst/udp_complete_inst/udp_64_inst/udp_checksum_gen_64_inst/udp_source_port_mem_reg" of size (depth=8 x width=16) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "core_inst/udp_complete_inst/udp_64_inst/udp_checksum_gen_64_inst/udp_dest_port_mem_reg" of size (depth=8 x width=16) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "core_inst/udp_complete_inst/udp_64_inst/udp_checksum_gen_64_inst/udp_checksum_mem_reg" of size (depth=8 x width=16) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-7030] Implemented Non-Cascaded Block Ram (cascade_height = 1) of width 36 for RAM "core_inst/udp_payload_fifo/mem_reg"
INFO: [Synth 8-7030] Implemented Non-Cascaded Block Ram (cascade_height = 1) of width 36 for RAM "core_inst/udp_payload_fifo/mem_reg"
INFO: [Synth 8-7030] Implemented Non-Cascaded Block Ram (cascade_height = 1) of width 2 for RAM "core_inst/udp_payload_fifo/mem_reg"
RAM Pipeline Warning: Read Address Register Found For RAM ip_addr_mem_reg. We will not be able to pipeline it. This may degrade performance.
RAM Pipeline Warning: Read Address Register Found For RAM valid_mem_reg. We will not be able to pipeline it. This may degrade performance.
---------------------------------------------------------------------------------
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:06:10 ; elapsed = 00:06:30 . Memory (MB): peak = 6320.484 ; gain = 3606.805 ; free physical = 37123 ; free virtual = 55021
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
Block RAM: Preliminary Mapping Report (see note below)
+--------------------------------------------------------------------------+-----------------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+-----------------+
|Module Name | RTL Object | PORT A (Depth x Width) | W | R | PORT B (Depth x Width) | W | R | Ports driving FF | RAMB18 | RAMB36 | Cascade Heights |
+--------------------------------------------------------------------------+-----------------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+-----------------+
|core_inst/eth_mac_10g_fifo_inst | tx_fifo/fifo_inst/mem_reg | 512 x 74(READ_FIRST) | W | | 512 x 74(WRITE_FIRST) | | R | Port A and B | 1 | 1 | |
|core_inst/eth_mac_10g_fifo_inst | rx_fifo/fifo_inst/mem_reg | 512 x 74(NO_CHANGE) | W | | 512 x 74(WRITE_FIRST) | | R | Port A and B | 1 | 1 | |
|core_inst/udp_complete_inst/\ip_complete_64_inst/arp_inst /arp_cache_inst | ip_addr_mem_reg | 512 x 32(READ_FIRST) | W | | 512 x 32(WRITE_FIRST) | | R | Port A and B | 1 | 0 | |
|core_inst/udp_complete_inst/\ip_complete_64_inst/arp_inst /arp_cache_inst | mac_addr_mem_reg | 512 x 48(READ_FIRST) | W | | 512 x 48(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |
|core_inst/udp_complete_inst/udp_64_inst | udp_checksum_gen_64_inst/payload_fifo/mem_reg | 256 x 74(READ_FIRST) | W | | 256 x 74(WRITE_FIRST) | | R | Port A and B | 1 | 1 | |
|core_inst/udp_payload_fifo | mem_reg | 1 K x 74(READ_FIRST) | W | | 1 K x 74(WRITE_FIRST) | | R | Port A and B | 1 | 2 | 1,1,1 |
+--------------------------------------------------------------------------+-----------------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+-----------------+
Note: The table above is a preliminary report that shows the Block RAMs at the current stage of the synthesis flow. Some Block RAMs may be reimplemented as non Block RAM primitives later in the synthesis flow. Multiple instantiated Block RAMs are reported only once.
Distributed RAM: Preliminary Mapping Report (see note below)
+--------------------------------------------------------------------------+--------------------------------------------------+-----------+----------------------+----------------+
|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives |
+--------------------------------------------------------------------------+--------------------------------------------------+-----------+----------------------+----------------+
|core_inst/udp_complete_inst/\ip_complete_64_inst/arp_inst /arp_cache_inst | valid_mem_reg | Implied | 512 x 1 | RAM256X1D x 2 |
|core_inst/udp_complete_inst/udp_64_inst | udp_checksum_gen_64_inst/udp_length_mem_reg | Implied | 8 x 16 | RAM32M16 x 2 |
|core_inst/udp_complete_inst/udp_64_inst | udp_checksum_gen_64_inst/ip_ttl_mem_reg | Implied | 8 x 8 | RAM32M16 x 1 |
|core_inst/udp_complete_inst/udp_64_inst | udp_checksum_gen_64_inst/ip_source_ip_mem_reg | Implied | 8 x 32 | RAM32M16 x 3 |
|core_inst/udp_complete_inst/udp_64_inst | udp_checksum_gen_64_inst/ip_dest_ip_mem_reg | Implied | 8 x 32 | RAM32M16 x 3 |
|core_inst/udp_complete_inst/udp_64_inst | udp_checksum_gen_64_inst/udp_source_port_mem_reg | Implied | 8 x 16 | RAM32M16 x 2 |
|core_inst/udp_complete_inst/udp_64_inst | udp_checksum_gen_64_inst/udp_dest_port_mem_reg | Implied | 8 x 16 | RAM32M16 x 2 |
|core_inst/udp_complete_inst/udp_64_inst | udp_checksum_gen_64_inst/udp_checksum_mem_reg | Implied | 8 x 16 | RAM32M16 x 2 |
+--------------------------------------------------------------------------+--------------------------------------------------+-----------+----------------------+----------------+
Note: The table above is a preliminary report that shows the Distributed RAMs at the current stage of the synthesis flow. Some Distributed RAMs may be reimplemented as non Distributed RAM primitives later in the synthesis flow. Multiple instantiated RAMs are reported only once.
---------------------------------------------------------------------------------
Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying XDC Timing Constraints
---------------------------------------------------------------------------------
WARNING: [Synth 8-3321] set_false_path : Empty to list for constraint at line 23 of /home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl. [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl:23]
WARNING: [Synth 8-3321] set_false_path : Empty to list for constraint at line 23 of /home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl. [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl:23]
---------------------------------------------------------------------------------
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:06:19 ; elapsed = 00:06:40 . Memory (MB): peak = 6320.484 ; gain = 3606.805 ; free physical = 36672 ; free virtual = 54570
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Timing Optimization
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Timing Optimization : Time (s): cpu = 00:06:23 ; elapsed = 00:06:44 . Memory (MB): peak = 6320.484 ; gain = 3606.805 ; free physical = 36611 ; free virtual = 54509
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
Block RAM: Final Mapping Report
+--------------------------------------------------------------------------+-----------------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+-----------------+
|Module Name | RTL Object | PORT A (Depth x Width) | W | R | PORT B (Depth x Width) | W | R | Ports driving FF | RAMB18 | RAMB36 | Cascade Heights |
+--------------------------------------------------------------------------+-----------------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+-----------------+
|core_inst/eth_mac_10g_fifo_inst | tx_fifo/fifo_inst/mem_reg | 512 x 74(READ_FIRST) | W | | 512 x 74(WRITE_FIRST) | | R | Port A and B | 1 | 1 | |
|core_inst/eth_mac_10g_fifo_inst | rx_fifo/fifo_inst/mem_reg | 512 x 74(NO_CHANGE) | W | | 512 x 74(WRITE_FIRST) | | R | Port A and B | 1 | 1 | |
|core_inst/udp_complete_inst/\ip_complete_64_inst/arp_inst /arp_cache_inst | ip_addr_mem_reg | 512 x 32(READ_FIRST) | W | | 512 x 32(WRITE_FIRST) | | R | Port A and B | 1 | 0 | |
|core_inst/udp_complete_inst/\ip_complete_64_inst/arp_inst /arp_cache_inst | mac_addr_mem_reg | 512 x 48(READ_FIRST) | W | | 512 x 48(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |
|core_inst/udp_complete_inst/udp_64_inst | udp_checksum_gen_64_inst/payload_fifo/mem_reg | 256 x 74(READ_FIRST) | W | | 256 x 74(WRITE_FIRST) | | R | Port A and B | 1 | 1 | |
|core_inst/udp_payload_fifo | mem_reg | 1 K x 74(READ_FIRST) | W | | 1 K x 74(WRITE_FIRST) | | R | Port A and B | 1 | 2 | 1,1,1 |
+--------------------------------------------------------------------------+-----------------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+-----------------+
Distributed RAM: Final Mapping Report
+--------------------------------------------------------------------------+--------------------------------------------------+-----------+----------------------+----------------+
|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives |
+--------------------------------------------------------------------------+--------------------------------------------------+-----------+----------------------+----------------+
|core_inst/udp_complete_inst/\ip_complete_64_inst/arp_inst /arp_cache_inst | valid_mem_reg | Implied | 512 x 1 | RAM256X1D x 2 |
|core_inst/udp_complete_inst/udp_64_inst | udp_checksum_gen_64_inst/udp_length_mem_reg | Implied | 8 x 16 | RAM32M16 x 2 |
|core_inst/udp_complete_inst/udp_64_inst | udp_checksum_gen_64_inst/ip_ttl_mem_reg | Implied | 8 x 8 | RAM32M16 x 1 |
|core_inst/udp_complete_inst/udp_64_inst | udp_checksum_gen_64_inst/ip_source_ip_mem_reg | Implied | 8 x 32 | RAM32M16 x 3 |
|core_inst/udp_complete_inst/udp_64_inst | udp_checksum_gen_64_inst/ip_dest_ip_mem_reg | Implied | 8 x 32 | RAM32M16 x 3 |
|core_inst/udp_complete_inst/udp_64_inst | udp_checksum_gen_64_inst/udp_source_port_mem_reg | Implied | 8 x 16 | RAM32M16 x 2 |
|core_inst/udp_complete_inst/udp_64_inst | udp_checksum_gen_64_inst/udp_dest_port_mem_reg | Implied | 8 x 16 | RAM32M16 x 2 |
|core_inst/udp_complete_inst/udp_64_inst | udp_checksum_gen_64_inst/udp_checksum_mem_reg | Implied | 8 x 16 | RAM32M16 x 2 |
+--------------------------------------------------------------------------+--------------------------------------------------+-----------+----------------------+----------------+
---------------------------------------------------------------------------------
Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Technology Mapping
---------------------------------------------------------------------------------
INFO: [Synth 8-7052] The timing for the instance core_inst/udp_complete_inst/ip_complete_64_inst/arp_inst/arp_cache_inst/ip_addr_mem_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance core_inst/udp_complete_inst/ip_complete_64_inst/arp_inst/arp_cache_inst/mac_addr_mem_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
---------------------------------------------------------------------------------
Finished Technology Mapping : Time (s): cpu = 00:06:26 ; elapsed = 00:06:47 . Memory (MB): peak = 6320.484 ; gain = 3606.805 ; free physical = 36610 ; free virtual = 54508
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished IO Insertion : Time (s): cpu = 00:06:29 ; elapsed = 00:06:50 . Memory (MB): peak = 6320.484 ; gain = 3606.805 ; free physical = 36610 ; free virtual = 54508
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Instances
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Instances : Time (s): cpu = 00:06:29 ; elapsed = 00:06:50 . Memory (MB): peak = 6320.484 ; gain = 3606.805 ; free physical = 36610 ; free virtual = 54508
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Rebuilding User Hierarchy
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:06:30 ; elapsed = 00:06:51 . Memory (MB): peak = 6320.484 ; gain = 3606.805 ; free physical = 36610 ; free virtual = 54508
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Ports
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Ports : Time (s): cpu = 00:06:30 ; elapsed = 00:06:51 . Memory (MB): peak = 6320.484 ; gain = 3606.805 ; free physical = 36610 ; free virtual = 54508
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:06:30 ; elapsed = 00:06:51 . Memory (MB): peak = 6320.484 ; gain = 3606.805 ; free physical = 36610 ; free virtual = 54508
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Nets
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Nets : Time (s): cpu = 00:06:30 ; elapsed = 00:06:51 . Memory (MB): peak = 6320.484 ; gain = 3606.805 ; free physical = 36610 ; free virtual = 54508
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Writing Synthesis Report
---------------------------------------------------------------------------------
Report BlackBoxes:
+------+-----------------+----------+
| |BlackBox name |Instances |
+------+-----------------+----------+
|1 |eth_xcvr_gt_full | 1|
+------+-----------------+----------+
Report Cell Usage:
+------+-----------------+------+
| |Cell |Count |
+------+-----------------+------+
|1 |eth_xcvr_gt_full | 1|
|2 |BUFG | 2|
|3 |CARRY8 | 74|
|4 |IBUFDS_GTE4 | 1|
|5 |LUT1 | 78|
|6 |LUT2 | 581|
|7 |LUT3 | 774|
|8 |LUT4 | 907|
|9 |LUT5 | 1076|
|10 |LUT6 | 2308|
|11 |MMCME4_BASE | 1|
|12 |MUXF7 | 10|
|13 |MUXF8 | 2|
|14 |RAM256X1D | 2|
|15 |RAM32M16 | 9|
|16 |RAM32X1D | 2|
|17 |RAMB18E2 | 5|
|21 |RAMB36E2 | 6|
|25 |FDCE | 1|
|26 |FDPE | 14|
|27 |FDRE | 4751|
|28 |FDSE | 260|
|29 |IBUF | 1|
|30 |IBUFGDS | 1|
|31 |OBUF | 9|
+------+-----------------+------+
---------------------------------------------------------------------------------
Finished Writing Synthesis Report : Time (s): cpu = 00:06:30 ; elapsed = 00:06:51 . Memory (MB): peak = 6320.484 ; gain = 3606.805 ; free physical = 36610 ; free virtual = 54508
---------------------------------------------------------------------------------
Synthesis finished with 0 errors, 0 critical warnings and 282 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:06:27 ; elapsed = 00:06:49 . Memory (MB): peak = 6324.395 ; gain = 3491.879 ; free physical = 42822 ; free virtual = 60720
Synthesis Optimization Complete : Time (s): cpu = 00:06:34 ; elapsed = 00:06:56 . Memory (MB): peak = 6324.395 ; gain = 3610.715 ; free physical = 42822 ; free virtual = 60720
INFO: [Project 1-571] Translating synthesized netlist
Netlist sorting complete. Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.09 . Memory (MB): peak = 6324.395 ; gain = 0.000 ; free physical = 42822 ; free virtual = 60720
INFO: [Netlist 29-17] Analyzing 104 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-570] Preparing netlist for logic optimization
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Opt 31-326] The CLKFBOUT to CLKFBIN net for instance clk_mmcm_inst with COMPENSATION=INTERNAL is optimized away to aid design routability
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 6344.496 ; gain = 0.000 ; free physical = 42766 ; free virtual = 60664
INFO: [Project 1-111] Unisim Transformation Summary:
A total of 18 instances were transformed.
BUFG => BUFGCE: 2 instances
IBUF => IBUF (IBUFCTRL, INBUF): 1 instance
IBUFGDS => IBUFDS (DIFFINBUF, IBUFCTRL): 1 instance
MMCME4_BASE => MMCME4_ADV: 1 instance
RAM256X1D => RAM256X1D (MUXF7(x4), MUXF8(x2), RAMD64E(x8)): 2 instances
RAM32M16 => RAM32M16 (RAMD32(x14), RAMS32(x2)): 9 instances
RAM32X1D => RAM32X1D (RAMD32(x2)): 2 instances
Synth Design complete, checksum: be18fea4
INFO: [Common 17-83] Releasing license: Synthesis
248 Infos, 198 Warnings, 0 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
synth_design: Time (s): cpu = 00:06:40 ; elapsed = 00:07:03 . Memory (MB): peak = 6344.496 ; gain = 3638.820 ; free physical = 42981 ; free virtual = 60878
INFO: [Common 17-1381] The checkpoint '/home/victor/verilog-ethernet/example/KR260/fpga/fpga/fpga.runs/synth_1/fpga.dcp' has been generated.
INFO: [runtcl-4] Executing : report_utilization -file fpga_utilization_synth.rpt -pb fpga_utilization_synth.pb
INFO: [Common 17-206] Exiting Vivado at Mon Mar 6 21:58:45 2023...
[Mon Mar 6 21:58:49 2023] synth_1 finished
wait_on_runs: Time (s): cpu = 00:06:53 ; elapsed = 00:07:17 . Memory (MB): peak = 2721.684 ; gain = 0.000 ; free physical = 45782 ; free virtual = 63658
INFO: [Common 17-206] Exiting Vivado at Mon Mar 6 21:58:49 2023...
echo "open_project fpga.xpr" > run_impl.tcl
echo "reset_run impl_1" >> run_impl.tcl
echo "launch_runs -jobs 4 impl_1" >> run_impl.tcl
echo "wait_on_run impl_1" >> run_impl.tcl
echo "open_run impl_1" >> run_impl.tcl
echo "report_utilization -file fpga_utilization.rpt" >> run_impl.tcl
echo "report_utilization -hierarchical -file fpga_utilization_hierarchical.rpt" >> run_impl.tcl
vivado -nojournal -nolog -mode batch -source run_impl.tcl
****** Vivado v2022.1 (64-bit)
**** SW Build 3526262 on Mon Apr 18 15:47:01 MDT 2022
**** IP Build 3524634 on Mon Apr 18 20:55:01 MDT 2022
** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
source run_impl.tcl
# open_project fpga.xpr
Scanning sources...
Finished scanning sources
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2022.1/data/ip'.
# reset_run impl_1
# launch_runs -jobs 4 impl_1
[Mon Mar 6 21:59:02 2023] Launched impl_1...
Run output will be captured here: /home/victor/verilog-ethernet/example/KR260/fpga/fpga/fpga.runs/impl_1/runme.log
# wait_on_run impl_1
[Mon Mar 6 21:59:02 2023] Waiting for impl_1 to finish...
*** Running vivado
with args -log fpga.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source fpga.tcl -notrace
****** Vivado v2022.1 (64-bit)
**** SW Build 3526262 on Mon Apr 18 15:47:01 MDT 2022
**** IP Build 3524634 on Mon Apr 18 20:55:01 MDT 2022
** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
source fpga.tcl -notrace
Command: link_design -top fpga -part xczu9eg-ffvb1156-2-e
Design is defaulting to srcset: sources_1
Design is defaulting to constrset: constrs_1
INFO: [Device 21-403] Loading part xczu9eg-ffvb1156-2-e
INFO: [Project 1-454] Reading design checkpoint '/home/victor/verilog-ethernet/example/KR260/fpga/fpga/fpga.gen/sources_1/ip/eth_xcvr_gt_full/eth_xcvr_gt_full.dcp' for cell 'sfp0_phy_inst/xcvr.eth_xcvr_gt_full_inst'
Netlist sorting complete. Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.06 . Memory (MB): peak = 2705.672 ; gain = 0.000 ; free physical = 44556 ; free virtual = 62432
INFO: [Netlist 29-17] Analyzing 106 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2022.1
INFO: [Project 1-570] Preparing netlist for logic optimization
Parsing XDC File [/home/victor/verilog-ethernet/example/KR260/fpga/fpga/fpga.gen/sources_1/ip/eth_xcvr_gt_full/synth/eth_xcvr_gt_full.xdc] for cell 'sfp0_phy_inst/xcvr.eth_xcvr_gt_full_inst/inst'
Finished Parsing XDC File [/home/victor/verilog-ethernet/example/KR260/fpga/fpga/fpga.gen/sources_1/ip/eth_xcvr_gt_full/synth/eth_xcvr_gt_full.xdc] for cell 'sfp0_phy_inst/xcvr.eth_xcvr_gt_full_inst/inst'
CRITICAL WARNING: [Designutils 20-1280] Could not find module 'eth_xcvr_gt_channel'. The XDC file /home/victor/verilog-ethernet/example/KR260/fpga/fpga/fpga.gen/sources_1/ip/eth_xcvr_gt_channel/synth/eth_xcvr_gt_channel.xdc will not be read for any cell of this module.
Parsing XDC File [/home/victor/verilog-ethernet/example/KR260/fpga/fpga.xdc]
CRITICAL WARNING: [Common 17-69] Command failed: 'Y6' is not a valid site or package pin name. [/home/victor/verilog-ethernet/example/KR260/fpga/fpga.xdc:29]
CRITICAL WARNING: [Vivado 12-1411] Cannot set LOC property of ports, the negative port (N-side) 'clk_125mhz_n' of a differential pair cannot be placed on a positive package pin 'Y5' (IOBM). [/home/victor/verilog-ethernet/example/KR260/fpga/fpga.xdc:30]
CRITICAL WARNING: [Common 17-69] Command failed: 'F8' is not a valid site or package pin name. [/home/victor/verilog-ethernet/example/KR260/fpga/fpga.xdc:38]
CRITICAL WARNING: [Vivado 12-1411] Cannot set LOC property of ports, Site location (GTHE4_COMMON_X1Y2) is not valid for the shape with the following elements:
led_OBUF[1]_inst
led[1]
[/home/victor/verilog-ethernet/example/KR260/fpga/fpga.xdc:39]
INFO: [Constraints 18-632] set_output_delay: No clock object specified, the clocks will be automatically identified [/home/victor/verilog-ethernet/example/KR260/fpga/fpga.xdc:48]
CRITICAL WARNING: [Common 17-69] Command failed: 'P16' is not a valid site or package pin name. [/home/victor/verilog-ethernet/example/KR260/fpga/fpga.xdc:55]
INFO: [Constraints 18-632] set_input_delay: No clock object specified, the clocks will be automatically identified [/home/victor/verilog-ethernet/example/KR260/fpga/fpga.xdc:58]
CRITICAL WARNING: [Common 17-69] Command failed: 'Y6' is not a valid site or package pin name. [/home/victor/verilog-ethernet/example/KR260/fpga/fpga.xdc:115]
CRITICAL WARNING: [Vivado 12-1411] Cannot set LOC property of ports, the negative port (N-side) 'sfp_mgt_refclk_0_n' of a differential pair cannot be placed on a positive package pin 'Y5' (IOBM). [/home/victor/verilog-ethernet/example/KR260/fpga/fpga.xdc:116]
INFO: [Constraints 18-632] set_output_delay: No clock object specified, the clocks will be automatically identified [/home/victor/verilog-ethernet/example/KR260/fpga/fpga.xdc:124]
Finished Parsing XDC File [/home/victor/verilog-ethernet/example/KR260/fpga/fpga.xdc]
Sourcing Tcl File [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/syn/vivado/eth_mac_fifo.tcl]
Inserting timing constraints for ethernet MAC with FIFO instance core_inst/eth_mac_10g_fifo_inst
WARNING: [Vivado 12-180] No cells matched '.*/rx_sync_reg_[1234]_reg\[\d+\]'. [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/syn/vivado/eth_mac_fifo.tcl:23]
WARNING: [Vivado 12-180] No cells matched '.*/tx_sync_reg_[1234]_reg\[\d+\]'. [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/syn/vivado/eth_mac_fifo.tcl:23]
Finished Sourcing Tcl File [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/syn/vivado/eth_mac_fifo.tcl]
Sourcing Tcl File [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl]
Inserting timing constraints for axis_async_fifo instance core_inst/eth_mac_10g_fifo_inst/rx_fifo/fifo_inst
INFO: [Timing 38-35] Done setting XDC timing constraints. [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl:23]
INFO: [Timing 38-2] Deriving generated clocks [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl:23]
Inserting timing constraints for axis_async_fifo instance core_inst/eth_mac_10g_fifo_inst/tx_fifo/fifo_inst
Finished Sourcing Tcl File [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl]
Sourcing Tcl File [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/lib/axis/syn/vivado/sync_reset.tcl]
Inserting timing constraints for sync_reset instance sync_reset_125mhz_inst
Inserting timing constraints for sync_reset instance sfp0_phy_inst/rx_reset_sync_inst
Inserting timing constraints for sync_reset instance sfp0_phy_inst/tx_reset_sync_inst
Finished Sourcing Tcl File [/home/victor/verilog-ethernet/example/KR260/fpga/lib/eth/lib/axis/syn/vivado/sync_reset.tcl]
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3075.621 ; gain = 0.000 ; free physical = 44271 ; free virtual = 62147
INFO: [Project 1-111] Unisim Transformation Summary:
A total of 15 instances were transformed.
IBUF => IBUF (IBUFCTRL, INBUF): 1 instance
IBUFGDS => IBUFDS (DIFFINBUF, IBUFCTRL): 1 instance
RAM256X1D => RAM256X1D (MUXF7(x4), MUXF8(x2), RAMD64E(x8)): 2 instances
RAM32M16 => RAM32M16 (RAMD32(x14), RAMS32(x2)): 9 instances
RAM32X1D => RAM32X1D (RAMD32(x2)): 2 instances
13 Infos, 2 Warnings, 8 Critical Warnings and 0 Errors encountered.
link_design completed successfully
link_design: Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 3075.621 ; gain = 369.949 ; free physical = 44271 ; free virtual = 62147
Command: opt_design
Attempting to get a license for feature 'Implementation' and/or device 'xczu9eg'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xczu9eg'
INFO: [Common 17-86] Your Implementation license expires in 15 day(s)
Running DRC as a precondition to command opt_design
Starting DRC Task
INFO: [DRC 23-27] Running DRC with 6 threads
INFO: [Project 1-461] DRC finished with 0 Errors
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 3131.648 ; gain = 48.023 ; free physical = 44268 ; free virtual = 62144
Starting Cache Timing Information Task
INFO: [Constraints 18-632] set_output_delay: No clock object specified, the clocks will be automatically identified [/home/victor/verilog-ethernet/example/KR260/fpga/fpga.xdc:48]
INFO: [Constraints 18-632] set_input_delay: No clock object specified, the clocks will be automatically identified [/home/victor/verilog-ethernet/example/KR260/fpga/fpga.xdc:58]
INFO: [Constraints 18-632] set_output_delay: No clock object specified, the clocks will be automatically identified [/home/victor/verilog-ethernet/example/KR260/fpga/fpga.xdc:124]
INFO: [Timing 38-35] Done setting XDC timing constraints.
Ending Cache Timing Information Task | Checksum: 17148b47b
Time (s): cpu = 00:00:00.38 ; elapsed = 00:00:00.16 . Memory (MB): peak = 3131.648 ; gain = 0.000 ; free physical = 44267 ; free virtual = 62143
Starting Logic Optimization Task
Phase 1 Retarget
INFO: [Opt 31-1287] Pulled Inverter core_inst/eth_mac_10g_fifo_inst/rx_fifo/fifo_inst/mem_reg_0_i_2 into driver instance core_inst/eth_mac_10g_fifo_inst/rx_fifo/fifo_inst/mem_reg_0_i_5, which resulted in an inversion of 14 pins
INFO: [Opt 31-1287] Pulled Inverter core_inst/udp_complete_inst/ip_complete_64_inst/arp_inst/arp_eth_rx_inst/cache_write_request_ip_reg[31]_i_1 into driver instance core_inst/udp_complete_inst/ip_complete_64_inst/arp_inst/arp_eth_rx_inst/outgoing_eth_dest_mac_reg[47]_i_5, which resulted in an inversion of 4 pins
INFO: [Opt 31-1287] Pulled Inverter core_inst/udp_payload_fifo/mem_reg_bram_0_i_1 into driver instance core_inst/udp_payload_fifo/mem_reg_bram_0_i_5, which resulted in an inversion of 3 pins
INFO: [Opt 31-1287] Pulled Inverter sfp0_phy_inst/phy_inst/eth_phy_10g_rx_inst/eth_phy_10g_rx_if_inst/eth_phy_10g_rx_watchdog_inst/error_count_reg[3]_i_2 into driver instance sfp0_phy_inst/phy_inst/eth_phy_10g_rx_inst/eth_phy_10g_rx_if_inst/eth_phy_10g_rx_watchdog_inst/serdes_rx_reset_req_reg_i_2, which resulted in an inversion of 5 pins
INFO: [Opt 31-138] Pushed 8 inverter(s) to 41 load pin(s).
INFO: [Opt 31-49] Retargeted 0 cell(s).
Phase 1 Retarget | Checksum: 1de3f1de0
Time (s): cpu = 00:00:00.5 ; elapsed = 00:00:00.24 . Memory (MB): peak = 3325.781 ; gain = 0.000 ; free physical = 44031 ; free virtual = 61907
INFO: [Opt 31-389] Phase Retarget created 4 cells and removed 16 cells
INFO: [Opt 31-1021] In phase Retarget, 15 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail.
Phase 2 Constant propagation
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Phase 2 Constant propagation | Checksum: 1dc2a1f98
Time (s): cpu = 00:00:00.56 ; elapsed = 00:00:00.29 . Memory (MB): peak = 3325.781 ; gain = 0.000 ; free physical = 44031 ; free virtual = 61907
INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 3 cells
Phase 3 Sweep
Phase 3 Sweep | Checksum: 1b9c272b5
Time (s): cpu = 00:00:00.66 ; elapsed = 00:00:00.4 . Memory (MB): peak = 3325.781 ; gain = 0.000 ; free physical = 44031 ; free virtual = 61907
INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 1 cells
Phase 4 BUFG optimization
INFO: [Opt 31-1077] Phase BUFG optimization inserted 0 global clock buffer(s) for CLOCK_LOW_FANOUT.
Phase 4 BUFG optimization | Checksum: 1b9c272b5
Time (s): cpu = 00:00:00.76 ; elapsed = 00:00:00.45 . Memory (MB): peak = 3325.781 ; gain = 0.000 ; free physical = 44030 ; free virtual = 61906
INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.
Phase 5 Shift Register Optimization
INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs
Phase 5 Shift Register Optimization | Checksum: 1b9c272b5
Time (s): cpu = 00:00:00.77 ; elapsed = 00:00:00.47 . Memory (MB): peak = 3325.781 ; gain = 0.000 ; free physical = 44030 ; free virtual = 61906
INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
Phase 6 Post Processing Netlist
Phase 6 Post Processing Netlist | Checksum: 1b9c272b5
Time (s): cpu = 00:00:00.79 ; elapsed = 00:00:00.48 . Memory (MB): peak = 3325.781 ; gain = 0.000 ; free physical = 44030 ; free virtual = 61906
INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
Opt_design Change Summary
=========================
-------------------------------------------------------------------------------------------------------------------------
| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations |
-------------------------------------------------------------------------------------------------------------------------
| Retarget | 4 | 16 | 15 |
| Constant propagation | 0 | 3 | 0 |
| Sweep | 0 | 1 | 0 |
| BUFG optimization | 0 | 0 | 0 |
| Shift Register Optimization | 0 | 0 | 0 |
| Post Processing Netlist | 0 | 0 | 0 |
-------------------------------------------------------------------------------------------------------------------------
Starting Connectivity Check Task
Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3325.781 ; gain = 0.000 ; free physical = 44030 ; free virtual = 61906
Ending Logic Optimization Task | Checksum: 1eda13495
Time (s): cpu = 00:00:00.94 ; elapsed = 00:00:00.56 . Memory (MB): peak = 3325.781 ; gain = 0.000 ; free physical = 44030 ; free virtual = 61906
Starting Power Optimization Task
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
INFO: [Constraints 18-632] set_output_delay: No clock object specified, the clocks will be automatically identified [/home/victor/verilog-ethernet/example/KR260/fpga/fpga.xdc:48]
INFO: [Constraints 18-632] set_input_delay: No clock object specified, the clocks will be automatically identified [/home/victor/verilog-ethernet/example/KR260/fpga/fpga.xdc:58]
INFO: [Constraints 18-632] set_output_delay: No clock object specified, the clocks will be automatically identified [/home/victor/verilog-ethernet/example/KR260/fpga/fpga.xdc:124]
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [Pwropt 34-9] Applying IDT optimizations ...
INFO: [Pwropt 34-10] Applying ODC optimizations ...
Running Vector-less Activity Propagation...
Finished Running Vector-less Activity Propagation
Starting PowerOpt Patch Enables Task
INFO: [Pwropt 34-162] WRITE_MODE attribute of 2 BRAM(s) out of a total of 11 has been updated to save power. Run report_power_opt to get a complete listing of the BRAMs updated.
INFO: [Pwropt 34-201] Structural ODC has moved 0 WE to EN ports
Number of BRAM Ports augmented: 3 newly gated: 2 Total Ports: 22
Ending PowerOpt Patch Enables Task | Checksum: 20fa69932
Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.06 . Memory (MB): peak = 5130.641 ; gain = 0.000 ; free physical = 43144 ; free virtual = 61020
Ending Power Optimization Task | Checksum: 20fa69932
Time (s): cpu = 00:00:25 ; elapsed = 00:00:25 . Memory (MB): peak = 5130.641 ; gain = 1804.859 ; free physical = 43177 ; free virtual = 61053
Starting Final Cleanup Task
Ending Final Cleanup Task | Checksum: 20fa69932
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 5130.641 ; gain = 0.000 ; free physical = 43177 ; free virtual = 61053
Starting Netlist Obfuscation Task
Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 5130.641 ; gain = 0.000 ; free physical = 43177 ; free virtual = 61053
Ending Netlist Obfuscation Task | Checksum: 24b6530be
Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 5130.641 ; gain = 0.000 ; free physical = 43177 ; free virtual = 61053
INFO: [Common 17-83] Releasing license: Implementation
48 Infos, 2 Warnings, 8 Critical Warnings and 0 Errors encountered.
opt_design completed successfully
opt_design: Time (s): cpu = 00:00:30 ; elapsed = 00:00:29 . Memory (MB): peak = 5130.641 ; gain = 2055.020 ; free physical = 43177 ; free virtual = 61053
INFO: [Constraints 18-632] set_output_delay: No clock object specified, the clocks will be automatically identified [/home/victor/verilog-ethernet/example/KR260/fpga/fpga.xdc:48]
INFO: [Constraints 18-632] set_input_delay: No clock object specified, the clocks will be automatically identified [/home/victor/verilog-ethernet/example/KR260/fpga/fpga.xdc:58]
INFO: [Constraints 18-632] set_output_delay: No clock object specified, the clocks will be automatically identified [/home/victor/verilog-ethernet/example/KR260/fpga/fpga.xdc:124]
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [Timing 38-480] Writing timing data to binary archive.
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:00.27 ; elapsed = 00:00:00.06 . Memory (MB): peak = 5130.641 ; gain = 0.000 ; free physical = 43161 ; free virtual = 61042
INFO: [Common 17-1381] The checkpoint '/home/victor/verilog-ethernet/example/KR260/fpga/fpga/fpga.runs/impl_1/fpga_opt.dcp' has been generated.
INFO: [runtcl-4] Executing : report_drc -file fpga_drc_opted.rpt -pb fpga_drc_opted.pb -rpx fpga_drc_opted.rpx
Command: report_drc -file fpga_drc_opted.rpt -pb fpga_drc_opted.pb -rpx fpga_drc_opted.rpx
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
INFO: [DRC 23-27] Running DRC with 6 threads
INFO: [Vivado_Tcl 2-168] The results of DRC are in file /home/victor/verilog-ethernet/example/KR260/fpga/fpga/fpga.runs/impl_1/fpga_drc_opted.rpt.
report_drc completed successfully
Command: place_design
Attempting to get a license for feature 'Implementation' and/or device 'xczu9eg'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xczu9eg'
INFO: [Common 17-86] Your Implementation license expires in 15 day(s)
INFO: [DRC 23-27] Running DRC with 6 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Running DRC as a precondition to command place_design
INFO: [DRC 23-27] Running DRC with 6 threads
ERROR: [DRC BIVB-1] Bank IO standard Support: Bank 66 has incompatible IO(s) because: The LVCMOS33 I/O standard is not supported for banks of type High Performance. Move the following ports or change their properties:
sfp0_tx_disable_b
ERROR: [DRC PLHDIO-5] HDIO DRC Checks: The following IO terminals need to be placed in HIGH_DENSITY IO banks (based on their IO standards), but they are incorrectly locked to non-HIGH_DENSITY IO banks. Please review and update the LOC constraints:
sfp0_tx_disable_b
CRITICAL WARNING: [DRC AVAL-326] Hard_block_must_have_LOC: The hard block IBUFDS_GTE4 cell ibufds_gte4_sfp_mgt_refclk_0_inst is missing a valid LOC constraint for placement assignment, normally supplied by IP generation or manually assigned using the LOC property. Unguided placement of this block may cause problems in routing or other issues. Please check your design and set a valid LOC for this block to avoid these problems.
INFO: [Vivado_Tcl 4-198] DRC finished with 2 Errors, 1 Critical Warnings
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
ERROR: [Vivado_Tcl 4-23] Error(s) found during DRC. Placer not run.
INFO: [Common 17-83] Releasing license: Implementation
67 Infos, 2 Warnings, 9 Critical Warnings and 3 Errors encountered.
place_design failed
ERROR: [Common 17-39] 'place_design' failed due to earlier errors.
INFO: [Common 17-206] Exiting Vivado at Mon Mar 6 21:59:56 2023...
[Mon Mar 6 21:59:57 2023] impl_1 finished
WARNING: [Vivado 12-8222] Failed run(s) : 'impl_1'
wait_on_runs: Time (s): cpu = 00:00:00.98 ; elapsed = 00:00:55 . Memory (MB): peak = 2721.680 ; gain = 0.000 ; free physical = 43139 ; free virtual = 61018
# open_run impl_1
ERROR: [Common 17-69] Command failed: Run 'impl_1' failed. Unable to open
INFO: [Common 17-206] Exiting Vivado at Mon Mar 6 21:59:57 2023...
make[1]: *** [../common/vivado.mk:115: fpga.runs/impl_1/fpga_routed.dcp] Error 1
make[1]: Leaving directory '/home/victor/verilog-ethernet/example/KR260/fpga/fpga'
make: *** [Makefile:14: fpga] Error 2-
-
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