Skip to content

Instantly share code, notes, and snippets.

@wnew
wnew / bram_wb.v
Created November 13, 2012 07:34
Parametrised BRAM wishbone bus interface
//============================================================================//
// //
// Parameterize BRAM with wishbone interface //
// //
// Module name: bram_wb //
// Desc: parameterized dual-port bram with a wishbone interface on one //
// port. //
// Date: June 2012 //
// Developer: Wesley New //
// Licence: GNU General Public License ver 3 //
@wnew
wnew / counter.v
Created November 13, 2012 07:16
Parametrised Verilog Counter
//============================================================================//
// //
// Parameterize Counter //
// //
// Module name: counter //
// Desc: parameterized counter, counts up/down in any increment //
// Date: Oct 2011 //
// Developer: Rurik Primiani & Wesley New //
// Licence: GNU General Public License ver 3 //
// Notes: //
@wnew
wnew / bram_sync_dp.v
Created October 25, 2012 13:36
Dual and Single Port Block RAMs with Synchronous read/writes/reset
//============================================================================//
// //
// Syncronous dual-port BRAM //
// //
// Module name: bram_sync_dp //
// Desc: parameterized, syncronous, inferable, true dual-port, //
// dual clock block ram //
// Date: Dec 2011 //
// Developer: Wesley New //
// Licence: GNU General Public License ver 3 //
//============================================================================//
// //
// Binary to Gray code converter //
// //
// Module name: bin2gray //
// Desc: parameterised module to convert binary numbers to gray encoded //
// numbers //
// Date: Aug 2012 //
// Developer: Wesley New //
// Licence: GNU General Public License ver 3 //