Created
November 13, 2012 07:16
-
-
Save wnew/4064449 to your computer and use it in GitHub Desktop.
Parametrised Verilog Counter
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
//============================================================================// | |
// // | |
// Parameterize Counter // | |
// // | |
// Module name: counter // | |
// Desc: parameterized counter, counts up/down in any increment // | |
// Date: Oct 2011 // | |
// Developer: Rurik Primiani & Wesley New // | |
// Licence: GNU General Public License ver 3 // | |
// Notes: // | |
// // | |
//============================================================================// | |
module counter #( | |
//============================== | |
// Top level block parameters | |
//============================== | |
parameter DATA_WIDTH = 8, // number of bits in counter | |
parameter COUNT_FROM = 0, // start with this number | |
parameter COUNT_TO = 2^(DATA_WIDTH-1), // value to count to in CL case | |
parameter STEP = 1 // negative or positive, sets direction | |
) ( | |
//=============== | |
// Input Ports | |
//=============== | |
input clk, | |
input en, | |
input rst, | |
//=============== | |
// Output Ports | |
//=============== | |
output reg [DATA_WIDTH-1:0] out | |
); | |
// Synchronous logic | |
always @(posedge clk) | |
begin | |
// if ACTIVE_LOW_RST is defined then reset on a low | |
// this should be defined on a system-wide basis | |
if ((`ifdef ACTIVE_LOW_RST rst `else !rst `endif) && out < COUNT_TO) | |
begin | |
if (en == 1) | |
begin | |
out <= out + STEP; | |
end | |
end | |
else | |
begin | |
out <= COUNT_FROM; | |
end // else: if(rst != 0) | |
end | |
endmodule |
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
//============================================================================// | |
// // | |
// Counter test bench // | |
// // | |
// Module name: counter_tb // | |
// Desc: runs and tests the counter module, and provides and interface // | |
// to test the module from Python (MyHDL) // | |
// Date: Oct 2011 // | |
// Developer: Rurik Primiani & Wesley New // | |
// Licence: GNU General Public License ver 3 // | |
// Notes: This only tests the basic functionality of the module, more // | |
// comprehensive testing is done in the python test file // | |
// // | |
//============================================================================// | |
module counter_tb; | |
//=================== | |
// local parameters | |
//=================== | |
localparam LOCAL_DATA_WIDTH = `ifdef DATA_WIDTH `DATA_WIDTH `else 8 `endif; | |
//============= | |
// local regs | |
//============= | |
reg clk; | |
reg en; | |
reg rst; | |
//============== | |
// local wires | |
//============== | |
wire [LOCAL_DATA_WIDTH-1:0] out; | |
//===================================== | |
// instance, "(d)esign (u)nder (t)est" | |
//===================================== | |
counter #( | |
.DATA_WIDTH (`ifdef DATA_WIDTH `DATA_WIDTH `else 8 `endif), | |
.COUNT_FROM (`ifdef COUNT_FROM `COUNT_FROM `else 0 `endif), | |
.COUNT_TO (`ifdef COUNT_TO `COUNT_TO `else 10 `endif), | |
.STEP (`ifdef STEP `STEP `else 1 `endif) | |
) dut ( | |
.clk (clk), | |
.en (en), | |
.rst (rst), | |
.out (out) | |
); | |
//============= | |
// initialize | |
//============= | |
initial | |
begin | |
$dumpvars; | |
clk = 0; | |
en = 1; | |
rst = 0; | |
#50 | |
en = 0; | |
#10 | |
en = 1; | |
end | |
//==================== | |
// simulate the clock | |
//==================== | |
always #1 | |
begin | |
clk = ~clk; | |
end | |
//=============== | |
// print output | |
//=============== | |
always @(posedge clk) $display(out); | |
//=============================== | |
// finish after 100 clock cycles | |
//=============================== | |
initial #100 $finish; | |
`endif | |
endmodule |
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
There is a mistake here. ^is doing an xor.
20: parameter COUNT_TO = 2^(DATA_WIDTH-1),
I think that must be:
parameter COUNT_TO = 1<<(DATA_WIDTH-1),